Open Core Protocol Debug Interface Specification rev 1.0 - OCP-IP

OCP-IP Confidential
1.2 OCP Debug strategy
The initial goal of the working group is to document a common set of Debug Guidelines and
signal models that address the range of simple to more complex debug of OCP based systems.
Many approaches are based on contributed prior art. Others identify new capabilities that are
needed for debug configurations and strategies that that incorporate embedded analysis that
comprehends multiple clock domains, power management domains, security domains, etc.
required in modern SoC and embedded systems design.
Where possible we leverage signals and interfaces defined in other OCP specifications. As an
example, JTAG signals as defined in OCP2.0 are initial primary debug interface. Due to
(largely bandwidth) limitations of JTAG for SoC debug, other options are presented where
possible, to enable alternatives. As example, for debug control interface, we discuss memory
mapped debug control options that use one of the embedded processors for debug configuration
and control as alternative to JTAG. Similarly, we discuss trace port interfaces (in the general
case, compatible with Nexus Interfaces as defined by IEEE 5001) as higher bandwidth parallel
trace port alternatives to JTAG serial interfaces.
1.3 Common guidelines and infrastructure
There are 2 preferred methods of mapping the registers of the debug IP-blocks - such that all
debug registers should be memory mapped to fit well into the usual programmer’s models and
allow for standard and extended testability concepts in manufacturing:
a. memory space mapping. – On-chip processor core can operate the debug blocks
b. JTAG mapped register access - controlled by external software debuggers over JTAG can
operate all debug IP-blocks
Comparative two-channel debugging with true time display of events is similar to the Logic
Analyzer philosophy. The time aligned display of system bus traces of data events from
different initiators on different buses is the main source of information. Setting of triggers on
any signals or combination of events from different cores, IP-blocks and firing assertions is
also basic to this idea. That is accomplished by the cross-trigger debug hardware block.
1.4 Scalability and configurability of debug resources
The OCP Debug Interface is following the general concept of master-slave request-response
philosophy to assure easy mapping of existing signaling schemes in the contemporary debug
interfaces to various cores and IP-blocks including assertions.
In general there will be two signal wrappers required on the hardware side: Between the core
and the debug interface to the OCP interconnect and between the OCP interconnect and any
existing debug infrastructure. Gradually debug infrastructures will be developed that connect
natively to the OCP Debug Interface.
The main idea of presenting it as a Debug Socket to the SoC designers is a structural
regularization to minimize errors in understanding of its functionality and to allow the
development of automatic checkers for this well defined debug interface.
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