Open Core Protocol Debug Interface Specification rev 1.0 - OCP-IP

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OCP-IP Confidential Many signals are flowing back to the debugger as feedback information or qualify/tag the data/instructions to explain the momentary context/status of the chip at the clock cycle moment of tracing. Debug bus transactor “Cerberus” accesses all memory mapped register data. Synchronous start of all cores is accomplished by pre-setting them before the start. A.2.2 JTAG Pins A.3 Debug Transactor – RUN Control Bus Master A basic bus transactor implementation would support only simple read and posted write data operations and may require stalling between operations to ensure synchronization of signaling operations (i.e. MData must occur concurrent with MDatavalid, SDataAccept occurs 36 of 62 © 2007 OCP-IP Association, All Rights Reserved.
OCP-IP Confidential concurrent with Sdata). More advanced OCP operations such as bursting may require additional (dedicated) logic, to support full speed bursting. Signal timing is shown in the OCP Standard timing diagrams. A transactor bus master operation can be initiated either from an external register load or from trigger output signals acting on specific bus monitoring operations. Address and data for individual bus transactions can also be written from the externally controlled registers, although this may be a slower manual process or require multiple cycles. Alternately, writing of regular (i.e. incrementing or other simple pattern) address and data can be controlled by counters or by logic enabled by trigger signals. Data and other OCP signals or performance data may also be traced (i.e. sequentially or periodically) with the bus master operations optionally stalled during JTAG data download phase, avoid loss of continuity. Additional trigger or state signals may be used for defining and controlling basic memory maps or domains. A.4 OCDS/MCDS Complete Example of Run Control: On-Chip Debug Support This chapter gives an overview of the debug features of the OCDS and MCDS. For detailed information about the On-Chip Debug Support (OCDS) and Multi Core Debug Solution (MCDS) please contact local Infineon representatives. This solution can be purchased as IP and proves that the signaling concept of the OCP Debug Socket is sufficient for trace and run control. In OCDS/MCDS we can find three levels of debug operation: OCDS Level 1 The OCDS Level 1 is mainly assigned for real-time software debugging purposes which have a demand for low-cost standard debugger hardware. The OCDS Level 1 is based on a JTAG interface that is used by the external debug hardware to communicate with the system. The on-chip Cerberus bus master module controls the interactions between the JTAG interface and the on-chip modules. The external debug hardware may become master of the internal buses, and read or write the on-chip register/memory resources. The Cerberus also makes it possible to define breakpoint and trigger conditions as well as to control user program execution (run/stop, break, single-step). 37 of 62 © 2007 OCP-IP Association, All Rights Reserved.
Page 1 and 2: OCP-IP Confidential Open Core Proto
Page 3 and 4: OCP-IP Confidential Table of Conten
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Page 9 and 10: OCP-IP Confidential to facilitate d
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Page 13 and 14: OCP-IP Confidential does place limi
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Page 19 and 20: OCP-IP Confidential in target trigg
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Page 25 and 26: OCP-IP Confidential Restarting core
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Page 33 and 34: OCP-IP Confidential Example 2. Wire
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Page 39 and 40: OCP-IP Confidential • Suspend fun
Page 41 and 42: OCP-IP Confidential A.4.1.5 BCU OCD
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Page 47 and 48: OCP-IP Confidential Bit Field Width
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Open Core Protocol Debug Interface Specification rev 1.0 - OCP-IP

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