Open Core Protocol Debug Interface Specification rev 1.0 - OCP-IP

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• Count within the [start, stop] window defined by triggers
• Effective cycles at the OCP target level
• Waiting cycles at OCP initiator level [latency; arbitration; shared link…..]
• Free cycles at the OCP target level
• Support continuous Performance monitoring [statistics]
• Export the computed performance statistics data through the “OCP Debug” to the “Trace
Export” component
• Preserve the OCP System bus behavior
• Be DVFS aware (D V F S)
The “Trace Export” component shall:
• Implement an elastic buffer
• Optionally build trace packets for different (MIPI/Nexus) protocols
• Allows SW instrumentation interleaving
4.2 System Time-stamping
For distributed systems, a timestamp provides the means of temporally correlating different
events that may be occurring in different systems or domains. There are many timestamp
implementations – the simplest is a gated clock and reset that can be used to run timestamp
counters at different blocks.
Table 4.2 OCP Debug Timestamp Interface Socket
TimeStamp
Interfaces Description Comment
ts_clk
Timestamp clock (gated version of
clk) for global on-chip
timestamping
global output
ts_reset Timestamp reset global output
4.2.1 Synchronous start of local time stamp counters
We rely on accurate distributed local time stamping to relax the trigger timing constraints. The
synchronized start of all local time stamp counters is important for the correct display of debug
events. Two simple concepts are proposed.
a. To make the counter reset arrive at the same time to all counters and the local clocks will
increment them. If all the local clocks are time aligned and multiple of each other then this
concept will work nicely. Else, this concept requires knowledge of the local clock frequencies
and the skew between them at the time of reset-release to work properly. Alternatively, stamp
counter reset can be de-asserted only at certain times when all clocks coincide with their rising
edge.
b. To make the reset of stamp counters happen without tight temporal restrictions but one
single clock goes to all counters at the same time (H-clock tree) and will be supplied only while
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