Open Core Protocol Debug Interface Specification rev 1.0 - OCP-IP

OCP-IP Confidential
A.4.1.5 BCU OCDS Level 1 (OCP Bus-Observer unit on the system bus)
The BCU on the FPI bus supports OCDS Level 1 and offers very comfortable and powerful
means for breakpoint generation. The BCU contains one comparator for
• the arbitration phase (look for specific bus master)
• the address phase (look for specific address or range)
• the data phase (look for read, write, supervisor mode, etc.)
The results can be combined to generate a break request signal, to be sent to the Break Switch
(Cross Trigger Block).
A.4.2 CPU or PCP OCDS Level 2 Trace
Every trace clock cycle, 16 bits of CPU/PCP trace information are sent out, representing the
current state of the CPU/PCP cores. The trace output lines are grouped into three parts:
• 5 bits of pipeline status information
• 8-bit indirect PC bus information
• 3 bits of breakpoint qualification information
With this information, an external emulator can reconstruct a cycle-by-cycle image of the
instruction flow through the CPU or PCP. The trace information can be captured by the
external debugger hardware and used to rebuild later on (off-line, using the source code)
a cycle accurate disassembly of the code that has been executed. It is also possible to
follow in real-time the current PC, facilitating advanced tools such as profilers, coverage
analysis tools etc.
The trace output port is controlled by the OSCU. The trace data can be output at CPU
clock speed (fTRCLK = fCPU). Trace clock can be higher if two cores are traced or a better
compression of trace data of all cores can keep this trace clock low.
A.4.3 Concurrent Debugging in Level 3 MCDS (Two Channel Tracing)
A concurrent debugging is possible when the control port is used as second channel and
ownership port is extended with process ID to differentiate between two sources that are traced.
The debug setup must define which two cores or IP-blocks were selected for concurrent
tracing.
41 of 62
© 2007 OCP-IP Association, All Rights Reserved.