Open Core Protocol Debug Interface Specification rev 1.0 - OCP-IP

OCP-IP Confidential
Control signals in case of gated clock domains and voltage domains in that the continuity and
functionality is not interrupted if any IP block on the bus switches off clocks or voltages. By
proper definition of the idle levels a blocking of the debug system shall not happen if one core
or IP block goes into sleep mode.
3.4 Cross Triggering Socket Interfaces
Information in MultiCore SoCs is complex and distributed such that global event cross
triggering and system level control for multi-core debug and triggering is often needed to
identify and isolate events occurring throughout the system. Event recognition and triggering is
widely used in conjunction with trace to capture information on events and operations in the
SoC. Conditions are monitored and compared to generate real time triggers in a Cross-trigger
Manager. These triggers in turn can be used to control event actions such as configuration,
breakpoints and trace collection. More complex implementations can be programmed to trigger
on specific values or sequences such as address regions and data read or write cycle types.
The cross-trigger block may be distributed to all IP connections to the OCP bus. If wiring is in
the OCP fabric then some pre-processing or wrappers (condition/action nodes) at each OCP
interface can be used to simplify the cross-trigger information. Wrappers can be programmed
via JTAG debugger (or native to a processor). Any block can send a trigger (edge or level) and
receive a trigger. Debugger or processor can configure specific trigger lines for each IP to send
a condition signal and from which trigger line it can receive a trigger/action).
CONCEPTUAL PICTURE (with two “trigger lines”)
Cross-Trigger signals in OCP fabric
Crosstrigger
Manager
Trigger_in_ condition[n:0]
Trigger_out_Action[n:0]
Config/Crtl lines
Trigger_out_enable[n:0]
Ext Trigger
JTAG IF
(x-trigger)
Trigger
IP Core Wrappers
Bus
Monitor
JTAG Trace IF
(block trace)
JTAG Debug IF
(core run ctrl)
(in OCP
Socket)
JTAG trace IF
(bus trace)
JTAG
Port
TAP
Figure 3.3: Cross-Trigger Block Diagram
Each trigger line consists of two uni-directional signals and one (optional) enable signal. A
minimum dual channel concept consists of two independent trigger lines, but as there is no
upper limit on number of cross-triggers realized in a design. The trigger line in, out, enable
may the result of logic combination of several signals for a given core. Trigger lines can be
connected directly to drive a bidirectional pin on the package and enable cross-triggering to
continue between several chips. External (off chip) triggers will be supported with pulse width
logic to interface external IO to the cross trigger manager.
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