Open Core Protocol Debug Interface Specification rev 1.0 - OCP-IP

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concurrent with Sdata). More advanced OCP operations such as bursting may require
additional (dedicated) logic, to support full speed bursting. Signal timing is shown in the OCP
Standard timing diagrams.
A transactor bus master operation can be initiated either from an external register load or from
trigger output signals acting on specific bus monitoring operations. Address and data for
individual bus transactions can also be written from the externally controlled registers,
although this may be a slower manual process or require multiple cycles. Alternately, writing
of regular (i.e. incrementing or other simple pattern) address and data can be controlled by
counters or by logic enabled by trigger signals. Data and other OCP signals or performance
data may also be traced (i.e. sequentially or periodically) with the bus master operations
optionally stalled during JTAG data download phase, avoid loss of continuity. Additional
trigger or state signals may be used for defining and controlling basic memory maps or
domains.
A.4 OCDS/MCDS Complete Example of Run Control: On-Chip Debug Support
This chapter gives an overview of the debug features of the OCDS and MCDS. For detailed
information about the On-Chip Debug Support (OCDS) and Multi Core Debug Solution
(MCDS) please contact local Infineon representatives. This solution can be purchased as IP and
proves that the signaling concept of the OCP Debug Socket is sufficient for trace and run
control. In OCDS/MCDS we can find three levels of debug operation:
OCDS Level 1
The OCDS Level 1 is mainly assigned for real-time software debugging purposes which
have a demand for low-cost standard debugger hardware.
The OCDS Level 1 is based on a JTAG interface that is used by the external debug hardware to
communicate with the system. The on-chip Cerberus bus master module controls the
interactions between the JTAG interface and the on-chip modules. The external debug
hardware may become master of the internal buses, and read or write the on-chip
register/memory resources. The Cerberus also makes it possible to define breakpoint and
trigger conditions as well as to control user program execution (run/stop, break, single-step).
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