Open Core Protocol Debug Interface Specification rev 1.0 - OCP-IP

OCP-IP Confidential
Restarting cores synchronously through the TAP is not difficult, since the TAP hardware has to
be only slightly extended by a synchronization technique (e.g., run-test-idle pass can
synchronize several cores in an ARM11 MP-Core).
Hardly any multicore architecture on the market implements SS by means of fetching and
executing exactly one instruction on every single core. Neither the heterogeneous (e.g. RISC +
DSP) nor the homogenous system (MultiCore PPC or ARM11MPCore) have cross-core SS
hardware-implementation as of today.
One favorite solution for this problem is "Virtual Single Stepping".
1. System is halted. Debugger reads/has the full state of all cores/memories
2. Run ca. 100-1000 cycles and halt then synchronously.
Trace during this time frame IP and all data accesses. (No problem with MCDS, even with a
small trace memory.)
3. With this information debugger can exactly reconstruct all states and data values between
start and end point
This means the user can then virtually single step forth and back (!) in this time window.
The timing relationship between the cores is as well maintained. There is possibly only a slight
impact at the start and the end of the period.
A similar solution is using an on-chip test platform with IEEE 1500 (developed by National
Cheng Kung University, Taiwan). For each core there is a register to trigger the halt then use
the 1500 scan chain to dump the core and memory. With the dump an ESL debugger can trace
the bug. When thinking about how to halt all cores simultaneously, although we like to
leverage test gates as much as possible, it seems additional debug gates are needed.
6. EDA and SW Tools Support
6.1 ESL Design and Design Checkers Support
The OCP Debug Interface, after selection of the debug signal groups, generates an XML
description text file that allows for easy modeling in the ESL abstracted chip design. This
XML file is the basic information for the automatic debug interface checkers.
The association of an XML interface file with a specific chip design is proposed to be an ID in
the JTAG interface readable by software level debuggers and EDA hardware level debuggers
that can access the XML file from a library maintained on the web. The ID must be at least 128
bits long or have a self-extensible format and size to be accepted by the world-wide chip
industry.
6.2 Programmers Model
We do not intend to include a programmer’s model for debug interactions into the OCP
standard. That is left to the vendors of the debug hardware blocks to satisfy the software DAS-
API interface requirements in providing and covering the minimum set of control sequences
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