Open Core Protocol Debug Interface Specification rev 1.0 - OCP-IP
Open Core Protocol Debug Interface Specification rev 1.0 - OCP-IP
Open Core Protocol Debug Interface Specification rev 1.0 - OCP-IP
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<strong>OCP</strong>-<strong>IP</strong> Confidential<br />
<strong>OCP</strong>- MCDS Wrappers<br />
2 debug channels A, B active<br />
out of N possible channels<br />
CH<strong>IP</strong><br />
PC Software<br />
<strong>OCP</strong> Data/Addr Socket<br />
<strong>OCP</strong> Data Wrapper<br />
Memory Mapped Access<br />
(can be extended for more than 2 channels)<br />
SYS<br />
<strong>Debug</strong><br />
MCDS<br />
<strong>Core</strong>1<br />
<strong>Core</strong>2<br />
<strong>Core</strong>3<br />
<strong>Debug</strong><br />
Regs<br />
<strong>Debug</strong><br />
Regs<br />
<strong>Debug</strong><br />
Regs<br />
<strong>OCP</strong> Trace Compress<br />
<strong>OCP</strong> <strong>Debug</strong> Wrapper<br />
<strong>OCP</strong> Interconnect<br />
<strong>OCP</strong>-Wrapper<br />
<strong>Core</strong> N<br />
… Dual Trace<br />
<strong>Core</strong> 1<br />
<strong>Core</strong> N<br />
… Cross Trigger<br />
<strong>Core</strong> 1<br />
Cerberus<br />
Run Control Socket<br />
Power, Security Socket<br />
Trace Socket<br />
Cross-Trigger Socket<br />
OSCU<br />
System Control<br />
JTAG <strong>Debug</strong> <strong>Interface</strong><br />
Multi-<strong>Core</strong> Break Switch<br />
Breakpoints, synchronized start/stop<br />
<strong>OCP</strong><br />
<strong>Debug</strong><br />
Socket<br />
TAP TRACE<br />
ICE<br />
BOX<br />
JTAG &<br />
TRACE<br />
(DAP)<br />
<strong>OCP</strong>-<strong>IP</strong> CONFIDENTIAL – NOT TO BE DUPLICATED 4<br />
Figure A.5 : <strong>OCP</strong>/MCDS Wrappers<br />
A B A B<br />
A B<br />
Trace<br />
A B<br />
JTAG API RDI<br />
USB<br />
Ethernet<br />
Parallel<br />
Serial<br />
<strong>Debug</strong> Server API<br />
<strong>Core</strong>1<br />
<strong>Debug</strong><br />
<strong>Core</strong>2<br />
<strong>Debug</strong><br />
<strong>Core</strong>3<br />
<strong>Debug</strong><br />
<strong>OCP</strong> <strong>Debug</strong> <strong>Interface</strong> and OSI-Model Borderlines<br />
OSI for <strong>Debug</strong> Information: PHYSICAL LAYER | TRANSPORT LAYER<br />
CH<strong>IP</strong><br />
CORE N<br />
CORE 1<br />
CORES <strong>OCP</strong>- INTERFACE <strong>OCP</strong>- INTERCONNECT <strong>OCP</strong>- INTERFACE REGISTER CUSTOM CUSTOM EXTERNAL JTAG<br />
TRANSFER DEBUG DEBUG INTERFACE<br />
PROTOCOL LOGIC REGISTERS TRACE<br />
- <strong>OCP</strong> DATA<br />
- <strong>OCP</strong> ADDRESS <strong>OCP</strong>-Bus<br />
MCDS MCDS MCDS INTERFACE<br />
- <strong>OCP</strong> CONTROL<br />
(SRESP, WIDTH, …) Observer<br />
Trace Regs<br />
or<br />
Bus Observer<br />
<strong>Core</strong><br />
<strong>Debug</strong> Regs<br />
TAP<br />
<strong>OCP</strong> - Wrapper<br />
- <strong>OCP</strong> DATA<br />
- <strong>OCP</strong> ADDRESS<br />
- <strong>OCP</strong> CONTROL<br />
(SRESP, WIDTH, …)<br />
4<br />
7<br />
10<br />
5<br />
8<br />
6<br />
9<br />
<strong>OCP</strong>-DATA<br />
SOCKET<br />
<strong>OCP</strong>-DATA<br />
SOCKET<br />
TAP<br />
<strong>OCP</strong>-<br />
JTAG<br />
<strong>OCP</strong>-<br />
TRACE<br />
<strong>OCP</strong>-TRIGGER<br />
<strong>OCP</strong>-RUN<br />
CONTROL<br />
EXT ENDED<br />
DEBUG<br />
SIGNALS<br />
10<br />
4<br />
5<br />
7<br />
8<br />
6<br />
9<br />
<strong>OCP</strong> - Wrapper<br />
Wrapper<br />
ch0<br />
ch1<br />
JTAG<br />
Data r/w<br />
Cross<br />
Trigger<br />
Run-<br />
Control<br />
<strong>OCP</strong> <strong>Debug</strong> Signal Classes and their Mapping on the MCDS <strong>Interface</strong><br />
Instruction Trace (data port / mode port)<br />
0 base address [31:0] / base_mode [2:0] = (idle, valid, forget, invalid);<br />
1 address increment [3:0] / inc_mode [2:0] = (idle, valid, forget, invalid);<br />
Data Trace (data port / mode port)<br />
2 address [31:0] / addr_mode [2:0] = (idle, valid, forget, invalid);<br />
3 data [31:0] / data_mode [2:0]=(idle, byte, h_word, word, d_word, forget, none, invalid);<br />
4 control [31:0] / control_mode [2:0] = (idle, write, read, forget);<br />
5 ownership id [7:0] / id_mode [2:0] = (idle, valid, forget, invalid);<br />
Bus-Trace<br />
Instructions<br />
Data<br />
MCDS<br />
SW-Register<br />
<strong>Interface</strong><br />
TAP TRACE<br />
JTAG<br />
3<br />
1<br />
2<br />
1<br />
2<br />
3<br />
CERBERUS<br />
Bus-Transactor<br />
TAP<br />
Manufacturing<br />
<strong>OCP</strong>-<strong>IP</strong> CONFIDENTIAL – NOT TO BE DUPLICATED<br />
Figure A.6 : <strong>OCP</strong> <strong>Debug</strong> <strong>Interface</strong> and OSI Model Borderlines. See page 35, 36, 41, 44.<br />
http://en.wikipedia.org/wiki/OSI_model<br />
45 of 62<br />
© 2007 <strong>OCP</strong>-<strong>IP</strong> Association, All Rights Reserved.
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