Open Core Protocol Debug Interface Specification rev 1.0 - OCP-IP

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OCP-IP Confidential Debug Data In TCODE & Message Control/ Formatting AUX In FSM AUX In Port Debug Data Out Debug Control Nexus Registers JTAG (IR/DR) Registers AUX Out FSM JTAG TAP FSM AUX Out Port JTAG Port AUX IO MCKO Figure C.2: Nexus Internal Architecture Description of Auxiliary Pins Message Clockout (MCKO) is a free-running output clock to tools for timing MDO and MSEO pin functions. MCKO can be independent of the embedded processor’s system clock or an embedded processor’s clock pin may be used as a functional equivalent for MCKO. MDO[M:0] Message Data Out (MDO[M:0]) are output pin(s) used for sending messages such as trace export and other read operations, memory substitution accesses, etc. Depending upon output bandwidth requirements, one, two, four, eight, or more pins may be implemented. MSEO[1:0] Message Start/End Out (MSEO [1:0]) are output pins that indicate when a message on the MDO pins has started, when a variable-length packet has ended, and when the message has ended. Only one MSEO pin is required, but two pins provide for more efficient transfers. EVTO Event Out (EVTO) is an optional output pin to development tools indicating exact timing for a single breakpoint status indication. Upon a breakpoint occurrence of the programmed breakpoint source, EVTO is asserted for a minimum of one clock period of MCKO. MCKI MDI[N:0] MSEI[1:0] EVTI RSTI Message Clockin (MCKI) is a free-running input clock from development tools for timing MDI and MSEI pin functions. MCKI can be independent of the embedded processor’s system clock. Message Data In (MDI[N:0]) are inputs used for downloading configuration data, writing to on chip resources, etc Depending upon input bandwidth requirements, multiple pins may be implemented. Message Start/End In (MSEI [1:0]) are inputs that indicate when a message on the MDI pins has started, when a variable-length packet has ended, and when the message has ended. Only one MSEI pin is required, but two pin implementations provide more efficient transfers. Event In (EVTI) is an input pin allowing off chip control such as processor halts (breakpoints) or synchronized Program/Data Messages Reset In (RSTI) is a pin for resetting the Nexus port resources. 58 of 62 © 2007 OCP-IP Association, All Rights Reserved.
OCP-IP Confidential C.2 Nexus Message Format Nexus architecture was designed based on a packet based messaging scheme, which supports debugging complex multicore systems and control of multicore debug processes using a transaction protocol (TCODE) that allows data to be sent in packets, using a packet header to provide information on the source and assumed destination of the data on-chip components as well as information on the subsequent data packets containing trace or other information. This simplifies interleaving of multiple trace sources and concurrent communication with multiple Nexus instruments. The Nexus specification defines a set of TCODEs for common identification and trace operations – including : • Program Trace: o Direct Branch o Indirect Branch o Indirect Branch With History o Synchronization o Resource Full o Repeat Branch o Repeat Instruction o Correlation • Data Trace: o Data Write o Data Read • Ownership Trace • Data Acquisition • Read/Write Access • Memory Substitution • Port Replacement • Watchpoint • Status User Defined TCODES can be defined by silicon or IP developers for debug features not covered in the standard, similarly to User Defined instruction features in JTAG. C.3 Nexus Debug Registers Nexus also defines a standard set of debug related on-chip registers, which facilitate the identification and interface to different cores and sub-systems and multicore control and debug operations. Standard definition and location of register set allows simpler integration and control of the instrumentations with embedded debuggers and related tools. Nexus defined recommended registers debug purposes include: • Device identification register (DID) • Client Select Register (CSC) • Development Control Register (DC) • Development Status Register (DS) • User Base Address Register (UBA) 59 of 62 © 2007 OCP-IP Association, All Rights Reserved.
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Open Core Protocol Debug Interface Specification rev 1.0 - OCP-IP

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