CHAPTER 3 METHODOLOGY 3.1 Overview The Water Monitoring ...

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Special Function RegistersA map of the on-chip memory area called the Special FunctionRegister (SFR) space is shown in Table 1.Note that not all of the addresses are occupied, and unoccupiedaddresses may not be implemented on the chip.Read accesses to these addresses will in general returnrandom data, and write accesses will have an indeterminateeffect.User software should not write 1s to these unlisted locations,since they may be used in future products to invokeTable 2. T2CON – Timer/Counter 2 Control RegisterT2CON Address = 0C8Hnew features. In that case, the reset or inactive values ofthe new bits will always be 0.Timer 2 Registers: Control and status bits are contained inregisters T2CON (shown in Table 2) and T2MOD (shown inTable 3) for Timer 2. The register pair (RCAP2H, RCAP2L)are the Capture/Reload registers for Timer 2 in 16-bit capturemode or 16-bit auto-reload mode.Interrupt Registers: The individual interrupt enable bitsare in the IE register. Two priorities can be set for each ofthe six interrupt sources in the IP register.Reset Value = 0000 0000BBit AddressableBit TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL27 6 5 4 3 2 1 0SymbolFunctionTF2 Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either RCLK = 1or TCLK = 1.EXF2 Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1.When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must becleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1).RCLKTCLKEXEN2TR2C/T2Receive clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in serial portModes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock.Transmit clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in serial portModes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.Timer 2 external enable. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if Timer2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX.Start/Stop control for Timer 2. TR2 = 1 starts the timer.Timer or counter select for Timer 2. C/T2 = 0 for timer function. C/T2 = 1 for external event counter (falling edge triggered).CP/RL2 Capture/Reload select. CP/RL2 = 1 causes captures to occur on negative transitions at T2EX if EXEN2 = 1. CP/RL2 = 0causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at T2EX when EXEN2 = 1. Wheneither RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.6AT89S52
AT89S52Table 3a. AUXR: Auxiliary RegisterAUXR Address = 8EH Reset Value = XXX00XX0BNot Bit Addressable– – – WDIDLE DISRTO – – DISALEBit 7 6 5 4 3 2 1 0– Reserved for future expansionDISALEDisable/Enable ALEDISALEOperating Mode0 ALE is emitted at a constant rate of 1/6 the oscillator frequency1 ALE is active only during a MOVX or MOVC instructionDISRTODisable/Enable Reset outDISRTO0 Reset pin is driven High after WDT times out1 Reset pin is input onlyWDIDLEDisable/Enable WDT in IDLE modeWDIDLE0 WDT continues to count in IDLE mode1 WDT halts counting in IDLE modeDual Data Pointer Registers: To facilitate accessing bothinternal and external data memory, two banks of 16-bitData Pointer Registers are provided: DP0 at SFR addresslocations 82H-83H and DP1 at 84H-85H. Bit DPS = 0in SFR AUXR1 selects DP0 and DPS = 1 selects DP1.The user should always initialize the DPS bit to theappropriate value before accessing the respective DataPointer Register.Power Off Flag: The Power Off Flag (POF) is located at bit4 (PCON.4) in the PCON SFR. POF is set to “1” duringpower up. It can be set and rest under software control andis not affected by reset.Table 3b. AUXR1: Auxiliary Register 1AUXR1 Address = A2H Reset Value = XXXXXXX0BNot Bit Addressable– – – – – – – DPSBit 7 6 5 4 3 2 1 0– Reserved for future expansionDPSData Pointer Register SelectDPS0 Selects DPTR Registers DP0L, DP0H1 Selects DPTR Registers DP1L, DP1H7
Page 1 and 2: CHAPTER 3METHODOLOGY3.1 OverviewThe
Page 3 and 4: 3.2.2 Analog To Digital Conversion
Page 5 and 6: Figure 3.5: Source Code for Convers
Page 7 and 8: 3.2.4 Water Monitoring System Circu
Page 9 and 10: 3.3 Programming.Programming is the
Page 11 and 12: ISP flash programmer in Figure 3.11
Page 13 and 14: The Visual Basic program will start
Page 15 and 16: Distance(cm)ReadingVoltage Trial1 (
Page 17 and 18: 4.2 Signal ConversionA sensor has s
Page 19 and 20: 4.3 User InterfaceBased on Table 4.
Page 21 and 22: Hardware DesignBasically, the const
Page 23 and 24: CHAPTER 5CONCLUSION5.1 SummaryWater
Page 25 and 26: This project can be expanded by usi
Page 27 and 28: APPENDICES41
Page 29 and 30: cjne a,volt,xsamejmp startxsame:mov
Page 31 and 32: xsame19:jnc more19mov dptr,#XVALIDc
Page 33 and 34: etrx:jnb ri,$clr rimov a,sbufretdel
Page 35 and 36: ElseShape8.FillColor = vbWhiteEnd I
Page 37 and 38: Private Sub Timer3_Timer()Label3.Ca
Page 39 and 40: APPENDIX EData Sheet AT89S5253
Page 41 and 42: Features• Compatible with MCS-51
Page 43 and 44: AT89S52Block DiagramP0.0 - P0.7P2.0
Page 45: AT89S52weakly pulled high. Setting
Page 49 and 50: AT89S52Watchdog Timer(One-time Enab
Page 51 and 52: AT89S52Figure 6. Timer 2 Auto Reloa
Page 53 and 54: AT89S52Baud Rate GeneratorTimer 2 i
Page 55 and 56: AT89S52Oscillator CharacteristicsXT
Page 57 and 58: AT89S52frequency should be less tha
Page 59 and 60: Figure 15. Flash Programming and Ve
Page 61 and 62: AT89S52Table 9. Serial Programming
Page 63 and 64: AT89S52Absolute Maximum Ratings*Ope
Page 65 and 66: AT89S52External Program Memory Read
Page 67 and 68: AT89S52Serial Port Timing: Shift Re
Page 69 and 70: Packaging Information44A, 44-lead,
Page 71 and 72: August 1997SemiconductorADC0802, AD
Page 73 and 74: ADC0802, ADC0803, ADC0804Absolute M
Page 75 and 76: ADC0802, ADC0803, ADC0804Electrical
Page 77 and 78: ADC0802, ADC0803, ADC0804Typical Pe
Page 79 and 80: ADC0802, ADC0803, ADC0804The device
Page 81 and 82: ADC0802, ADC0803, ADC0804V IN ±5VR
Page 83 and 84: ADC0802, ADC0803, ADC0804Figures 19
Page 85 and 86: ADC0802, ADC0803, ADC0804IRQ (4)†

CHAPTER 3 METHODOLOGY 3.1 Overview The Water Monitoring ...

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