CHAPTER 3 METHODOLOGY 3.1 Overview The Water Monitoring ...

Programming Interface – Parallel ModeEvery code byte in the Flash array can be programmed byusing the appropriate combination of control signals. Thewrite operation cycle is self-timed and once initiated, willautomatically time itself to completion.Table 8. Flash Programming ModesAll major programming vendors offer worldwide support forthe Atmel microcontroller series. Please contact your localprogramming vendor for the appropriate software revision.Mode V CC RST PSENALE/PROGEA/V PP P2.6 P2.7 P3.3 P3.6 P3.7P0.7-0DataP2.4-0AddressP1.7-0Write Code Data 5V H L(2)12V L H H H H D IN A12-8 A7-0Read Code Data 5V H L H H L L L H H D OUT A12-8 A7-0Write Lock Bit 1 5V H L(3)12V H H H H H X X XWrite Lock Bit 2 5V H L(3)12V H H H L L X X XWrite Lock Bit 3 5V H L(3)12V H L H H L X X XRead Lock Bits1, 2, 35V H L H H H H L H LP0.2,P0.3,P0.4XXChip Erase 5V H L(1)12V H L H L L X X XRead Atmel ID 5V H L H H L L L L L 1EH X 0000 00HRead Device ID 5V H L H H L L L L L 52H X 0001 00HRead Device ID 5V H L H H L L L L L 06H X 0010 00HNotes: 1. Each PROG pulse is 200 ns - 500 ns for Chip Erase.2. Each PROG pulse is 200 ns - 500 ns for Write Code Data.3. Each PROG pulse is 200 ns - 500 ns for Write Lock Bits.4. RDY/BSY signal is output on P3.0 during programming.5. X = don’t care.Figure 13. Programming the Flash Memory(Parallel Mode)A0 - A7ADDR.0000H/1FFFHA8 - A12SEE FLASHPROGRAMMINGMODES TABLE3-33 MHzP1.0-P1.7P2.0 - P2.4P2.6P2.7P3.3P3.6AT89S52P3.7XTAL2V CCP0ALEEAP3.0VCCPGMDATAPROGV IH/VPPRDY/BSYFigure 14. Verifying the Flash Memory (Parallel Mode)ADDR.0000H/1FFFHSEE FLASHPROGRAMMINGMODES TABLE3-33 MHzA0 - A7A8 - A12P1.0-P1.7P2.0 - P2.4P2.6P2.7AT89S52P3.3P3.6P3.7XTAL 2V CCP0ALEEAV CCPGM DATA(USE 10KPULLUPS)V IHXTAL1RSTV IHXTAL1RSTV IHGNDPSENGNDPSEN18AT89S52