Memory OrganizationMCS-51 devices have a separate address space for Programand Data Memory. Up to 64K bytes each of externalProgram and Data Memory can be addressed.Program MemoryIf the EA pin is connected to GND, all program fetches aredirected to external memory.On the AT89S52, if EA is connected to V CC , programfetches to addresses 0000H through 1FFFH are directed tointernal memory and fetches to addresses 2000H throughFFFFH are to external memory.Data Memory<strong>The</strong> AT89S52 implements 256 bytes of on-chip RAM. <strong>The</strong>upper 128 bytes occupy a parallel address space to theSpecial Function Registers. This means that the upper 128bytes have the same addresses as the SFR space but arephysically separate from SFR space.When an instruction accesses an internal location aboveaddress 7FH, the address mode used in the instructionspecifies whether the CPU accesses the upper 128 bytesof RAM or the SFR space. Instructions which use directaddressing access of the SFR space.For example, the following direct addressing instructionaccesses the SFR at location 0A0H (which is P2).MOV 0A0H, #dataInstructions that use indirect addressing access the upper128 bytes of RAM. For example, the following indirectaddressing instruction, where R0 contains 0A0H, accessesthe data byte at address 0A0H, rather than P2 (whoseaddress is 0A0H).MOV @R0, #dataNote that stack operations are examples of indirectaddressing, so the upper 128 bytes of data RAM are availableas stack space.8AT89S52
AT89S52Watchdog Timer(One-time Enabled with Reset-out)<strong>The</strong> WDT is intended as a recovery method in situationswhere the CPU may be subjected to software upsets. <strong>The</strong>WDT consists of a 13-bit counter and the Watchdog TimerReset (WDTRST) SFR. <strong>The</strong> WDT is defaulted to disablefrom exiting reset. To enable the WDT, a user must write01EH and 0E1H in sequence to the WDTRST register(SFR location 0A6H). When the WDT is enabled, it willincrement every machine cycle while the oscillator is running.<strong>The</strong> WDT timeout period is dependent on the externalclock frequency. <strong>The</strong>re is no way to disable the WDTexcept through reset (either hardware reset or WDT overflowreset). When WDT overflows, it will drive an outputRESET HIGH pulse at the RST pin.Using the WDTTo enable the WDT, a user must write 01EH and 0E1H insequence to the WDTRST register (SFR location 0A6H).When the WDT is enabled, the user needs to service it bywriting 01EH and 0E1H to WDTRST to avoid a WDT overflow.<strong>The</strong> 13-bit counter overflows when it reaches 8191(1FFFH), and this will reset the device. When the WDT isenabled, it will increment every machine cycle while theoscillator is running. This means the user must reset theWDT at least every 8191 machine cycles. To reset theWDT the user must write 01EH and 0E1H to WDTRST.WDTRST is a write-only register. <strong>The</strong> WDT counter cannotbe read or written. When WDT overflows, it will generate anoutput RESET pulse at the RST pin. <strong>The</strong> RESET pulseduration is 96xTOSC, where TOSC=1/FOSC. To make thebest use of the WDT, it should be serviced in those sectionsof code that will periodically be executed within thetime required to prevent a WDT reset.WDT During Power-down and IdleIn Power-down mode the oscillator stops, which means theWDT also stops. While in Power-down mode, the userdoes not need to service the WDT. <strong>The</strong>re are two methodsof exiting Power-down mode: by a hardware reset or via alevel-activated external interrupt which is enabled prior toentering Power-down mode. When Power-down is exitedwith hardware reset, servicing the WDT should occur as itnormally does whenever the AT89S52 is reset. ExitingPower-down with an interrupt is significantly different. <strong>The</strong>interrupt is held low long enough for the oscillator to stabilize.When the interrupt is brought high, the interrupt isserviced. To prevent the WDT from resetting the devicewhile the interrupt pin is held low, the WDT is not starteduntil the interrupt is pulled high. It is suggested that theWDT be reset during the interrupt service for the interruptused to exit Power-down mode.To ensure that the WDT does not overflow within a fewstates of exiting Power-down, it is best to reset the WDTjust before entering Power-down mode.Before going into the IDLE mode, the WDIDLE bit in SFRAUXR is used to determine whether the WDT continues tocount if enabled. <strong>The</strong> WDT keeps counting during IDLE(WDIDLE bit = 0) as the default state. To prevent the WDTfrom resetting the AT89S52 while in IDLE mode, the usershould always set up a timer that will periodically exit IDLE,service the WDT, and reenter IDLE mode.With WDIDLE bit enabled, the WDT will stop to count inIDLE mode and resumes the count upon exit from IDLE.UART<strong>The</strong> UART in the AT89S52 operates the same way as theUART in the AT89C51 and AT89C52. For further informationon the UART operation, refer to the ATMEL Web site(http://www.atmel.com). From the home page, select ‘Products’,then ‘8051-Architecture Flash Microcontroller’, then‘Product <strong>Overview</strong>’.Timer 0 and 1Timer 0 and Timer 1 in the AT89S52 operate the same wayas Timer 0 and Timer 1 in the AT89C51 and AT89C52. Forfurther information on the timers’ operation, refer to theATMEL Web site (http://www.atmel.com). From the homepage, select ‘Products’, then ‘8051-Architecture FlashMicrocontroller’, then ‘Product <strong>Overview</strong>’.Timer 2Timer 2 is a 16-bit Timer/Counter that can operate as eithera timer or an event counter. <strong>The</strong> type of operation isselected by bit C/T2 in the SFR T2CON (shown in Table 2).Timer 2 has three operating modes: capture, auto-reload(up or down counting), and baud rate generator. <strong>The</strong>modes are selected by bits in T2CON, as shown in Table 3.Timer 2 consists of two 8-bit registers, TH2 and TL2. In theTimer function, the TL2 register is incremented everymachine cycle. Since a machine cycle consists of 12 oscillatorperiods, the count rate is 1/12 of the oscillatorfrequency.Table 3. Timer 2 Operating ModesRCLK +TCLK CP/RL2 TR2 MODE0 0 1 16-bit Auto-reload0 1 1 16-bit Capture1 X 1 Baud Rate GeneratorX X 0 (Off)9
- Page 1 and 2: CHAPTER 3METHODOLOGY3.1 OverviewThe
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- Page 5 and 6: Figure 3.5: Source Code for Convers
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- Page 29 and 30: cjne a,volt,xsamejmp startxsame:mov
- Page 31 and 32: xsame19:jnc more19mov dptr,#XVALIDc
- Page 33 and 34: etrx:jnb ri,$clr rimov a,sbufretdel
- Page 35 and 36: ElseShape8.FillColor = vbWhiteEnd I
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- Page 39 and 40: APPENDIX EData Sheet AT89S5253
- Page 41 and 42: Features• Compatible with MCS-51
- Page 43 and 44: AT89S52Block DiagramP0.0 - P0.7P2.0
- Page 45 and 46: AT89S52weakly pulled high. Setting
- Page 47: AT89S52Table 3a. AUXR: Auxiliary Re
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- Page 53 and 54: AT89S52Baud Rate GeneratorTimer 2 i
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- Page 61 and 62: AT89S52Table 9. Serial Programming
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- Page 75 and 76: ADC0802, ADC0803, ADC0804Electrical
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