CHAPTER 3 METHODOLOGY 3.1 Overview The Water Monitoring ...

AT89S52Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively,of an inverting amplifier that can be configured for use asan on-chip oscillator, as shown in Figure 11. Either a quartzcrystal or ceramic resonator may be used. To drive thedevice from an external clock source, XTAL2 should be leftunconnected while XTAL1 is driven, as shown in Figure 12.There are no requirements on the duty cycle of the externalclock signal, since the input to the internal clocking circuitryis through a divide-by-two flip-flop, but minimum and maximumvoltage high and low time specifications must beobserved.Idle ModeIn idle mode, the CPU puts itself to sleep while all the onchipperipherals remain active. The mode is invoked bysoftware. The content of the on-chip RAM and all the specialfunctions registers remain unchanged during thismode. The idle mode can be terminated by any enabledinterrupt or by a hardware reset.Note that when idle mode is terminated by a hardwarereset, the device normally resumes program executionfrom where it left off, up to two machine cycles before theinternal reset algorithm takes control. On-chip hardwareinhibits access to internal RAM in this event, but access tothe port pins is not inhibited. To eliminate the possibility ofan unexpected write to a port pin when idle mode is terminatedby a reset, the instruction following the one thatinvokes idle mode should not write to a port pin or to externalmemory.Power-down ModeIn the Power-down mode, the oscillator is stopped, and theinstruction that invokes Power-down is the last instructionexecuted. The on-chip RAM and Special Function Registersretain their values until the Power-down mode is terminated.Exit from Power-down mode can be initiated eitherby a hardware reset or by an enabled external interrupt.Reset redefines the SFRs but does not change the on-chipRAM. The reset should not be activated before V CC isrestored to its normal operating level and must be heldactive long enough to allow the oscillator to restartand stabilize.Figure 11. Oscillator ConnectionsC2C1XTAL2XTAL1GNDNote: C1, C2 = 30 pF ± 10 pF for Crystals= 40 pF ± 10 pF for Ceramic ResonatorsFigure 12. External Clock Drive ConfigurationNCEXTERNALOSCILLATORSIGNALXTAL2XTAL1GNDTable 6. Status of External Pins During Idle and Power-down ModesMode Program Memory ALE PSEN PORT0 PORT1 PORT2 PORT3Idle Internal 1 1 Data Data Data DataIdle External 1 1 Float Data Address DataPower-down Internal 0 0 Data Data Data DataPower-down External 0 0 Float Data Data Data15