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Figure 5 – Co-simulation library – cosim_ex_hwcosim_lib – created by the post-generation script. When System Generator implements a model in hardware, it uses a single clock source to drive the design. Multi-rate blocks are supported by using derived clock enables. These clock enables have periods that are integer multiples of the period of the system clock. Data traveling in and out of the hardware also has a period that is a multiple of the system clock period. These multiples, or ratios, between the port data rates and the system clock rate are stored in the co-simulation block by the compilation block script when it is instantiated. A co-simulation block must be driven by ports with data rates equivalent to the gateway data rates of the original subsystem. The block automatically adjusts its output ports to run at the appropriate rates. If the block detects an incorrect input port rate, it will generate an error message. The easiest way to ensure that an input port has the appropriate rate is to drive the co-simulation port with the same signal that drove the original subsystem port or gateway. Hardware Clocking There are many possible synchronization techniques for the interface between FPGA hardware and Simulink. One technique uses a single-step clock to keep the hardware in lockstep with the software simulation. This is achieved by providing a single clock pulse to the hardware for each simulation cycle. Using this technique enables you to perform incremental design and verification. On the other hand, the single-step clock technique has its disadvantages. When it is used for clocking the FPGA design, the communication overhead between hardware and Simulink can severely limit the effective processing rate in some designs. This condition is exacerbated by bus latency. Simulation speed can be greatly increased by allowing the hardware to process more than one set of input samples at a time. One way to accomplish this is to provide a freerunning clock to the design under test. Use an explicit synchronization mechanism such as a flag implemented as a memory-mapped register to coordinate data transfers between Simulink and the hardware. The inputs and Figure 6 – Co-simulation block parameterized with port names that match the original model. Figure 7 – A co-simulation block can be driven by either Xilinx fixed-point or double signal types. outputs of the design are written to and sampled asynchronously. Benchmarks When using a single-step clock, speedups of seven to 50 times are typically achieved. The demos that come with System Generator were used as benchmarks. The results are shown in Table 1. Referring to the table, the bit error rate (BER) tester was created to test forward error correction (FEC) blocks. A freerunning clock source achieved a speedup of six orders of magnitude. The data source for the BER tester was an LFSR in the FPGA. The test is started, and after some time when a “done” flag is set, you can read the results from the FPGA and display them in Simulink. Conclusion System Generator hardware co-simulation provides you with a simple but powerful method of incorporating hardware co-simulation in Simulink and System Generator models. The hardware co-simulation flow automates the entire hardware implementation process. You have more time to focus on the design itself. Once the hardware co-simulation software has produced a co-simulation block, it can be used just like any other System Generator block in a model. To learn more about System Generator for DSP, go to www.xilinx. com/system_generator/ and click on “System Generator for DSP.” Application Software Simulation Time Hardware Execution Time Speedup 5x5 Image Filter 170 sec 4 sec 43x Cordic Arc Tangent 187 sec 27 sec 7x Additive White Gaussian 600 sec 80 sec 7.5x Noise Channel (AWGN) Table 1 – Benchmark results for hardware-in-the-loop co-simulation 10 Xcell Journal Fall 2003
Get Physical with the PALACE Synthesis Solution Aplus Design Technologies’ PALACE physical synthesis tool can drive down your costs by helping you quickly meet or exceed your design requirements with a slower speed grade or a smaller device. by Sheldon D’Paiva Applications Engineer Aplus Design Technologies sdpaiva@aplus-dt.com Xilinx Spartan-3 FPGAs give designers advanced features at previously unattainable costs. Moreover, Spartan-3 densities reaching five million system gates provide cost-competitive solutions in markets once only addressable by ASICs. But as FPGAs penetrate the ASIC space, FPGA designers must deal with the same complexities faced by ASIC designers. In particular, ASIC designers know that to meet design requirements and reduce iterations within the design flow, synthesis must be coupled with physical design considerations. Synthesis design flows that do not take physical design into account can erode your time to market and cost advantages. With the large densities and complexities of modern low-cost FPGA architectures such as Spartan-3 FPGAs, you cannot afford to ignore interconnect delay and architecturespecific considerations during synthesis. Poorly synthesized designs cause greatly increased runtimes for the place-and-route tools, as they struggle to meet timing constraints. Bad designs also create an additional burden on the designer by requiring expert manual intervention and timeconsuming iterations between synthesis and implementation tools. Furthermore, additional costs are incurred if the design requirements are not met in the targeted device. For highvolume and low-density devices, moving to a faster speed grade typically translates to a 13% increase in cost; moving to a larger part translates to a 16% increase in cost. This increase in cost is even greater for lower volume designs or when using higher density devices. Fall 2003 Xcell Journal 11
Page 1 and 2: ISSUE 47, FALL 2003 XCELL JOURNAL X
Page 3 and 4: EDITOR IN CHIEF Carlis Collins edit
Page 5 and 6: View from the top Innovation, Educa
Page 7 and 8: High Density Spartan-3 Support ISE
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Page 15 and 16: Integration of Functions Glue Logic
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Develop Applications Right Out of t
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Take the Titanium Solution Xilinx T
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Support and Titanium Technical Serv
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Celoxica, IBM, Mentor Graphics, Nal
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Xilinx AllianceCORE Third-Party IP
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Mikrokrets AS www.mikrokrets.no/ FP
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XILINX CPLD http://www.xilinx.com/p
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XILINX VIRTEX-II SERIES FPGAs http:
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XILINX SPARTAN FPGAs http://www.xil
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XILINX CONFIGURATION STORAGE SOLUTI
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XILINX IP REFERENCE GUIDE Function
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Avoid messy timing mistakes. Use Me
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