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10 Gigabit Ethernet Designs Many features of the Avnet Virtex-II Pro development board, shown in Figure 1, are especially useful to support 10 Gigabit Ethernet designs. The Virtex-II Pro device, an XC2VP20-FF896, provides the logic capacity needed for 10 Gigabit MAC and other supporting IP cores. Extensive on-board memory provides sufficient storage for both code and data space for the embedded IBM PowerPC processors found on the Virtex-II Pro device. High-speed interface functions using the RocketIO features of the Virtex-II Pro Platform FPGA are supported on the board with a variety of XPAK 10 GE or OC192 SFP SFP HSSDC2 HSSDC2 Kit does not include modules SODIMM DDRSDRAM Micron MT8VDDT1664HDG-265B2 SDRAM (32 MB) Micron MT48V8M16LFFF-8 System ACE CF AvBus Buffers 2 MB SRAM (PCI Memory Space) Cypress CY7C1062AV33-12BGC FLASH (16 MB) Figure 2 – Development board block diagram standard connectors. Xilinx IP cores provide the logic functions required to implement the physical and logical layers of common serial communications standards. A detailed block diagram of the board is shown in Figure 2. The development board has enough memory devices to support even a complex design. Memory support includes: • Micron DDR SDRAM SODIMM (128 MB expandable to 1 GB) • Micron Mobile SDRAM (two 8 Mb x 16 Mb devices, 32 MB total) • Cypress Asynchronous SRAM (512 Kb x 32 Kb, 2 MB total) Switches Rocket I/O A Single XPAK and a Combination of Two SFP and Two HSSDC2 Connectors Virtex-II Pro Xilinx SelectMAP PCI Bridge Xilinx XC2S300E- 6FG456C Voltage Clamp PCI Edge Connector • Intel StrataFlash (16 MB total) • CompactFlash card • Configuration memory using Xilinx PROM XC18V02-VQ44 and the Xilinx System ACE CF solution. With 1 GB of high-speed DDR SDRAM memory, bandwidth will not be a bottleneck for most 10 Gigabit Ethernet applications. The board supports a variety of highspeed interface standards. These include: • A standard XPAK module (located on the back of the board) that can implement either a 10 Gigabit Ethernet port or an OC-192 serial interface 10/100/1000 Ethernet PHY National Semiconductor DP83865BVH PROM Xilinx XC18V02VQ44C 62 Xcell Journal Fall 2003 PMC 32-bit (50) AvBus Console RS-232 Clock Clocks (4) Switches (6) Power Supply National Semiconductor LP3966ES LM2636MTC DB9 Right Angle LEDs 7-Seg + Row of 8
• Two HSSDC2 connectors for implementing InfiniBand or Fibre Channel interfaces • Two small form-factor pluggable (SFP) modules for implementing Gigabit Ethernet, Fibre Channel, or InfiniBand protocols. These interfaces can be used in conjunction with RocketIO transceivers on the Virtex-II Pro device and the appropriate Xilinx IP cores to implement the desired serial interface standard. A bridging or switch application could use one or more of these ports as the other end to a 10 Gigabit Ethernet interface. Expansion of the basic features of the board is possible by using the PCI bus or the four 140-pin general purpose connectors (AvBus connectors). A variety of AvBuscompatible boards, from Avnet and third parties, provide even more hardware options. A Speedy Start In addition to the extensive hardware features described above, the kit comes with a variety of supporting documentation and design files to make it easy to get started. The kit ships with a detailed user manual, quick start guide, and an extensive board support package that includes a full-featured Linux kernel, PCI bus, and memory drivers. Several demonstration examples show how to best use the features of the Virtex-II Pro device and interface it to additional devices on the development board. Two of the projects are PowerPCbased and give examples of memory interfaces – one for an OPB interface and one for a PLB interface. Another example project is RocketIObased and illustrates the use of a custom peripheral to allow PowerPC access to the multi-gigabit transceiver (MGT) at 3.125 Gbps. Implementing 10 Gigbit Ethernet Several of the design considerations in the development kit will be common to any Virtex-II Pro-based design and are shared here. On our design, the MGTs of the Virtex-II Pro Platform FPGA are connected to two HSSDC2 connectors, two SFP ADS-XLX-V2PRO-DEVP7-5 (Populated with XC2VP7, –5 speed grade) $1,995 ADS-XLX-V2PRO-DEVP7-6 (Populated with XC2VP7, –6 speed grade) $2,495 ADS-XLX-V2PRO-DEVP20-5 (Populated with XC2VP20, –5 speed grade) $2,995 ADS-XLX-V2PRO-DEVP20-6 (Populated with XC2VP20, –6 speed grade) $3,495 Table 1 – Part numbers and prices of the Avnet Virtex-II Pro development kit connectors with EMI cages, and pads for an XPAK host connector with mounting holes for the mid-board module holder. In the case of the two HSSDC2 and two SFP connections, the MGTs were treated individually. This means that the lengths of the transmit and receive signals were matched per MGT but not matched to any other MGT. However, in the case of the XPAK interface, four MGT channels were bonded together to create the 10 Gigabit Attachment Unit Interface (XAUI). The four transmit pairs and the four receive pairs have matched lengths. The XPAK is a SFP transceiver module for 10 Gbps serial data transmission. The XPAK interface on the board was designed to run at the IEEE 10GBASE-R optical rate of 10.3125 Gbps with a four-lane electrical interface at 3.125 Gbps (XAUI interface). This interface requires the –6 speed grade Virtex-II Pro device and the use of the Xilinx 10 Gigabit Ethernet MAC core. The XPAK interface on the Virtex-II Pro development board complies with the XPAK MSA (multi-source agreement) Revision 2.1 (except for the programmable supply, which is implemented via jumpers). The XPAK MSA closely resembles the XENPAK MSA and makes frequent references to it. The XPAK form factor was used because it is half the size of a XENPAK, does not require a large cutout in the PCB, and has a mid-board mounting option, allowing the module to be placed anywhere on the board instead of on the faceplate. The 156.25 MHz differential clock input is used for the reference clock to the MGT macro. Because the phase-locked loop of the MGT always multiplies by a factor of 20, using the 156.25 MHz clock results in a transmission rate of 3.125 Gbps. The transmit and receive signals are directly connected to the XPAK host connector or are DC-coupled. However, all XPAK-compliant modules have AC coupling on both the transmit and receive signals inside the module itself. The transmit differential pairs are routed on the solder side of the board, while the receive pairs are routed on the component side. This keeps the signals from crossing on the way to the XPAK connector. The analog ground planes in the layers directly adjacent to the outer layers provide the return paths. The analog ground planes are separated from the digital ground used for the rest of the components on the board, but are referenced to digital ground in several locations through ferrite beads. More design details like these are documented in the user guide, design files, and example designs included with the development kit. Conclusion The Avnet Virtex-II Pro development kit is designed with real applications in mind. It has all of the features demanded by this class of application – a large FPGA, extensive memory, and standards-based flexible high-speed serial ports, as well as considerable expansion capability. The kit should enable a faster time to market for your next 10 Gigabit or other high-speed embedded design. The Avnet Virtex-II Pro development kit is available now. See Table 1 for available Virtex-Pro devices and board prices. Contact your local Avnet sales office to get detailed ordering information and to talk to an Avnet FAE about your specific design need. Fall 2003 Xcell Journal 63
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ISSUE 47, FALL 2003 XCELL JOURNAL X
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EDITOR IN CHIEF Carlis Collins edit
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View from the top Innovation, Educa
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High Density Spartan-3 Support ISE
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compilation block from the XtremeDS
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