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Logging and Telemetry The VCM logs around 220 channels of data at rates as high as 1 KHz. As many as 90 of these channels are signals from sensors used to analyze the car’s performance over an entire race or test distance. Some channels monitor the actions of the control software, while others monitor the driver’s inputs. An example of the logged data is shown in Figure 2. Each of the Stage 5 VCMs fitted to the two FW25 cars of drivers Juan Montoya and Ralf Schumacher can log 256 MB of data generated by the cars during a race. This data is stored on a standard, commercial Compact- Flash (CF) card mounted permanently inside the VCM, which provides convenient and costeffective non-volatile storage. The CF card contents are downloaded by wire link after the race for analysis. A subsection of the logged data is also transmitted via serial link to a telemetry transmitter on the car. This transmits the data in real time back to the garage where it is displayed on a PC, enabling technicians to monitor a car’s performance from the pit. Failure Analysis and Reporting Embedded in the VCM are functions to detect failures of sensors on board the car. The output of these routines prevents failed sensors from being used by the control algorithms, and allows problems to be identified quickly. The failure of a small sensor cannot be allowed to ruin a driver’s race. To prevent this, the VCM monitors inputs from multiple sensors and acts on the majority decision in each case. The level of redundancy is determined according to the importance of the function, the vulnerability of the sensor, and the potential weight penalty. The VCM is capable of monitoring as many as 100 input sensors, while controlling numerous hydraulic systems. This failure detection capability is aug- mented by pit-to-car telemetry. The race engineer can arbitrate against a sensor or set of sensors believed to be providing inaccurate signals. Figure 2 – Data from more than 90 sensors monitor the car’s performance. Extra Processing Horsepower BMW’s engine designers would say that a racing car can never have too much horsepower. BMW WilliamsF1’s electronic designers have a similar opinion about processing capability: More MIPS (million instructions per second) allow them to consolidate functions within the VCM, control more aspects of the car, and use more sophisticated models to generate accurate control signals. Despite the rule-makers’ attempts to simplify and reduce the cost of F1 technology, the processing demands on the VCM continue on a steeply upward trend. Paradoxically, rule changes for 2004 prohibiting pit-to-car telemetry, which are intended to reduce the complexity of electronics, will drive the processing load higher in future years. The decision-making performed by human operators in the garage must now migrate to the car itself. Dave Walker and his team are faced with an ever-increasing demand for processing power. But they do not enjoy a corresponding increase in thermal budget or physical size limits. The growing list of duties for the VCM, originally used only as a pure data logger, has increased processing requirements. Hardware Solution With 220 channels to monitor, as well as numerous control algorithms to execute, Dave Walker says processor cycles are far too precious to waste on basic input functions, such as filtering or controlling Ato-D conversions. Among the potential solutions to reducing processor load, the BMW WilliamsF1 team did not favor a microcontroller because of the need to write software and maintain the code base. In addition, the software inspection demands imposed by the FIA make the use of a microcontroller even less desirable. A pure hardware solution is more optimal, according to Walker. Before the advent of modern multi-MFLOP (mega floating-point operations per second) DSPs, it was only possible to meet the timing demands for data logging and controlling high-speed hydraulic actuators by using hardware to accelerate certain functions. The team has used field programmable gate arrays from a variety of vendors since the first-generation design, but BMW WilliamsF1 has now been working exclusively with Xilinx for a number of years. The current Stage 5 VCM uses the Xilinx Virtex-E XCV600-E FPGA alongside a Texas Instruments DSP. Although processing capabilities of DSPs have advanced dramatically since the first versions of VCM entered service, the team finds the hardware processing capabilities of the companion FPGA a valuable resource, which allows it to focus on using the DSP for pure number crunching. There will never be a surfeit of processing power, as this can always be consumed by the increasingly sophisticated models provided to the VCM. These models demand more accurate control outputs for gearbox, differential management, and communications with the engine. Today’s XCV600-E is around 85% utilized. The 48 Xcell Journal Fall 2003
team plans to migrate to a more complex, next-generation Virtex-II Pro FPGA in the VCM incarnation for 2004. The team also plans to use Xilinx Titanium and Platinum technical support packages, which will include on-site design and training by expert Xilinx engineers. Accordingly, the sixth-generation BMW WilliamsF1 VCM will perform even more processing, with a more powerful DSP chip alongside a more complex Xilinx FPGA. The Virtex-II Pro platform FPGA will also be able to offload additional DSP functions by virtue of its onboard multiplyand-accumulate (MAC) block to deliver a greater boost in effective system MIPS. For 2004, the Virtex-II Pro device will host new programmable filtering and communication protocol control functions. The platform FPGAs will also manage UARTs and PWMs (pulse-width modulators) that were formerly implemented in separate components on the printed circuit board. This ability to progressively soak extra discrete logic into the FPGA – at the same time as assimilating software routines – has enabled the VCM’s footprint to shrink significantly over its lifetime. Conclusion For those determined to win, Formula 1 has always demanded the utmost speed and nimbleness – not only on the racecourse, but also in terms of technical innovation. Rule changes introduced at the start of 2003 have taxed all teams’ abilities to respond quickly and effectively. At the vehicle control level, engineers must to be able to add and remove functional blocks from the VCM within a short timeframe to meet FIA regulations. The teams must also be able to incorporate performance modifications as the current season progresses. Fast feature swapping – combined with the ability to consolidate more of the low-level hardware and discrete logic into an FPGA to save weight, space, and power dissipation – is crucial to BMW WilliamsF1’s ability to demonstrate compliance with FIA rules. Moreover, Xilinx FPGA reprogramability enables the team to innovate quickly to maintain a competitive edge over rival teams. To learn more about the Xilinx partnership with the BMW WilliamsF1 team, go to www.bmw.williamsf1.com and click on “Xilinx Joins the Team” under Partner News. To get the latest Formula 1 standings, go to www.formula1.com. As of this writing (July 8), the BMW WilliamsF1 team had back-to-back wins, taking first and second place at both the European Grand Prix at Nurburgring and the French Grand Prix at Magny-Cours. Earlier this year, the team posted its first win of the season in the Monte-Carlo Grand Prix at Monaco. According to a July 7 Formula 1 press release: “Williams has suddenly vaulted past both McLaren and Ferrari to establish itself as the team most in form ... If proof were needed of the growing Williams menace, in the last five races McLaren, initially the 2003 series leader, has scored 34 points; Ferrari has scored 55; and Williams has scored 70.” In overall standings, BMW WilliamsF1 was trailing the series leader Ferrari by just three points. Fall 2003 Xcell Journal 49
Page 1 and 2: ISSUE 47, FALL 2003 XCELL JOURNAL X
Page 3 and 4: EDITOR IN CHIEF Carlis Collins edit
Page 5 and 6: View from the top Innovation, Educa
Page 7 and 8: High Density Spartan-3 Support ISE
Page 9 and 10: compilation block from the XtremeDS
Page 11 and 12: Get Physical with the PALACE Synthe
Page 13 and 14: You can control PALACE operations i
Page 15 and 16: Integration of Functions Glue Logic
Page 17 and 18: 4. Support for Xilinx V2PDK Softwar
Page 19 and 20: Resulting PAR Fmax LUT Count 135 12
Page 21 and 22: points. The ability to support many
Page 23 and 24: Get the Platform Flash PROMise Redu
Page 25 and 26: implemented. This means that there
Page 27 and 28: • Synchronizing Logic - At this s
Page 29 and 30: 64 Light Sensors LOAD Although this
Page 31 and 32: The DQS net could potentially be de
Page 33 and 34: Design Security Consider the philos
Page 35 and 36: Bitstream Encryption Simple Encrypt
Page 37 and 38: System Challenges The differing req
Page 39 and 40: nVisage captures it all As a profes
Page 41 and 42: A unique, scientific research instr
Page 43 and 44: utes, and seconds, the “counter a
Page 45 and 46: cisely 0-1-0-1, the cell’s fitnes
Page 47: y Liza Boland System Architect, Con
Page 51 and 52: ands on the market. We use a 73.768
Page 53 and 54: Boeing Harnesses Virtex-II Pro Plat
Page 55 and 56: straints make it very hard for embe
Page 57 and 58: oss The Board. Avnet Design Servic
Page 59 and 60: To give you a good jump-start on de
Page 61 and 62: Develop Applications Right Out of t
Page 63 and 64: • Two HSSDC2 connectors for imple
Page 65 and 66: y Jim Beneke Director of Technical
Page 67 and 68: User Application and Bluetooth Prot
Page 69 and 70: from one fabrication line to anothe
Page 71 and 72: Take the Titanium Solution Xilinx T
Page 73 and 74: Support and Titanium Technical Serv
Page 75: Celoxica, IBM, Mentor Graphics, Nal
Page 78 and 79: Xilinx AllianceCORE Third-Party IP
Page 80 and 81: XPERTS Partners 3T BV www.3T.nl/ De
Page 82 and 83: Mikrokrets AS www.mikrokrets.no/ FP
Page 85 and 86: XILINX CPLD http://www.xilinx.com/p
Page 87 and 88: XILINX VIRTEX-II SERIES FPGAs http:
Page 89 and 90: XILINX SPARTAN FPGAs http://www.xil
Page 91 and 92: XILINX CONFIGURATION STORAGE SOLUTI
Page 93 and 94: XILINX IP REFERENCE GUIDE Function
Page 99 and 100:
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