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In some cases the PTT button is replaced by a voice activity detector, which has an inherent turn-on delay, meaning that the beginning of your transmission will always be lost. To eliminate loss at the beginning of transmissions, we combined a PCM codec with a static RAM to implement a digital audio delay line, which holds up the voice signal (Figure 4). The PCM data transfers in to and out of the codec over a high-speed 2.048 MHz serial bus (Figure 5). Encoded PCM samples are converted to parallel data and written into a ring buffer in the RAM. By reading parallel data from the RAM location with a fixed offset (modulo the size of the ring buffer) to the write address, the output is delayed. The parallel data is then reconverted and fed into the codec over a serial bus. in analog out Figure 5 – Codec to RAM interface block diagram Figure 4 – Digital audio delay line One PCM sample reads/writes every 125 microseconds. The delay can be adjusted by modifying the read-to-write address offset. These operations, in particular the emulation of the serial bus, cannot be performed by a standard microprocessor, which would be too slow. We chose a Xilinx CoolRunner-II device with 64 macrocells for the interface between the codec and the RAM. This solves our speed problem and also saves PCB real estate that would have otherwise been taken by standard logic components. The Development Process Excellent support from Impact Memec, the local Xilinx representative, kept the development start-up time extremely short. We used ISE WebPACK software for all of the designs, and found it espe- delay D(7:0) AD(12:0) A codec 2.048 Mb CoolRunner-II RAM control cially helpful for the following reasons: • Access to error messages on the Xilinx website provided instant in-depth information about the particular message, often with hints on how to solve the problem. • The designs were simulated using ModelSim XE Starter, leading to some design modifications and allowing flaws to be fixed early in the development process. Some problems were due to signal spikes on clock lines, which were properly indicated by the simulator. All designs loaded and operated correctly on the first attempt when moved to the target hardware. We have no doubt that the design environment of the Xilinx CoolRunner-II family of CPLDs is mature and sound. Conclusion Xilinx CoolRunner-II devices are well suited for our applications. They provide a reliable technical solution combined with a short development time and a low start-up cost. Based on this positive experience, Girsberger Elektronik AG is planning to incorporate Xilinx CoolRunner-II devices in such products as: • The upgrade and replacement of an old avalanche beacon ASIC to eliminate the high NRE cost. • A beacon to locate stolen cars. By taking over part of the training transmitter CPLD design, we will save significant development time. • A data over voice interface for use on ISDN B-channels. The CPLD beats the speed of any microprocessor in manipulating the bitstream on an industry-standard IOM bus. Although CPLDs are often associated with high speed or high density, Xilinx CoolRunner-II devices are an interesting alternative for small-scale applications in which top speed and high density are not key concerns. For more information about Girsberger Elektronik AG, visit www.girsberger-elektronik.ch/. 52 Xcell Journal Fall 2003
Boeing Harnesses Virtex-II Pro Platform for Image Processing Designing a state-of-the-art airborne imaging system requires massive parallel processing, high-speed I/Os, and heavy-duty signal processing. Boeing’s design team found all three plus configurability in the Virtex-II Pro Platform FPGA. by Christopher Musial Real Time Systems Engineer The Boeing Co. christopher.j.musial@boeing.com Katie DaCosta Solutions Marketing Manager, DSP Solutions Xilinx, Inc. katie.dacosta@xilinx.com Over the past 10 years, the aerospace industry has adopted the use of commercial off-the-shelf (COTS) electronics in favor of developing custom systems. This change has been fueled in part by the high development costs associated with ASICs or specialized software processors. As a result, commercial suppliers seeking the best available technology have focused on the design and fabrication of multi-processor hardware. Today, many of these systems feature DSP devices or RISC-based CPUs. Although Boeing has successfully integrated these solutions into many systems, the application of COTS to high-end signal- and image-processing designs has remained very challenging. Even “high-end” DSP and RISC architectures offer limited parallelism, memory flexibility, interface capability, and determinism. The integration of dozens of processors in a hard real-time architecture is non-trivial. The complications of packaging, weight, volume, thermal management, and power consumption to system design are obvious. The challenges often appear to grow exponentially with the number of processors required to solve the problem. The advent of Virtex-II Pro Platform FPGAs and the promise of more advanced, future Platform FPGAs are completely changing the game of programmable system design. Airborne Imaging Boeing is designing a state-of-the-art airborne, electro-optical imaging system. The end product will provide exceptional surveillance and engagement capability for aircraft in the 21st century. To achieve these objectives, Boeing designers are integrating a broad array of technologies into a complete programmable system. Key design elements include: • A high-resolution gimbaled telescope is driven by line-of-sight control electron- Summer 2003 Xcell Journal 53
Page 1 and 2: ISSUE 47, FALL 2003 XCELL JOURNAL X
Page 3 and 4: EDITOR IN CHIEF Carlis Collins edit
Page 5 and 6: View from the top Innovation, Educa
Page 7 and 8: High Density Spartan-3 Support ISE
Page 9 and 10: compilation block from the XtremeDS
Page 11 and 12: Get Physical with the PALACE Synthe
Page 13 and 14: You can control PALACE operations i
Page 15 and 16: Integration of Functions Glue Logic
Page 17 and 18: 4. Support for Xilinx V2PDK Softwar
Page 19 and 20: Resulting PAR Fmax LUT Count 135 12
Page 21 and 22: points. The ability to support many
Page 23 and 24: Get the Platform Flash PROMise Redu
Page 25 and 26: implemented. This means that there
Page 27 and 28: • Synchronizing Logic - At this s
Page 29 and 30: 64 Light Sensors LOAD Although this
Page 31 and 32: The DQS net could potentially be de
Page 33 and 34: Design Security Consider the philos
Page 35 and 36: Bitstream Encryption Simple Encrypt
Page 37 and 38: System Challenges The differing req
Page 39 and 40: nVisage captures it all As a profes
Page 41 and 42: A unique, scientific research instr
Page 43 and 44: utes, and seconds, the “counter a
Page 45 and 46: cisely 0-1-0-1, the cell’s fitnes
Page 47 and 48: y Liza Boland System Architect, Con
Page 49 and 50: team plans to migrate to a more com
Page 51: ands on the market. We use a 73.768
Page 55 and 56: straints make it very hard for embe
Page 57 and 58: oss The Board. Avnet Design Servic
Page 59 and 60: To give you a good jump-start on de
Page 61 and 62: Develop Applications Right Out of t
Page 63 and 64: • Two HSSDC2 connectors for imple
Page 65 and 66: y Jim Beneke Director of Technical
Page 67 and 68: User Application and Bluetooth Prot
Page 69 and 70: from one fabrication line to anothe
Page 71 and 72: Take the Titanium Solution Xilinx T
Page 73 and 74: Support and Titanium Technical Serv
Page 75: Celoxica, IBM, Mentor Graphics, Nal
Page 78 and 79: Xilinx AllianceCORE Third-Party IP
Page 80 and 81: XPERTS Partners 3T BV www.3T.nl/ De
Page 82 and 83: Mikrokrets AS www.mikrokrets.no/ FP
Page 85 and 86: XILINX CPLD http://www.xilinx.com/p
Page 87 and 88: XILINX VIRTEX-II SERIES FPGAs http:
Page 89 and 90: XILINX SPARTAN FPGAs http://www.xil
Page 91 and 92: XILINX CONFIGURATION STORAGE SOLUTI
Page 93 and 94: XILINX IP REFERENCE GUIDE Function
Page 99 and 100: Avoid messy timing mistakes. Use Me

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