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Put Hardware in the Loop with Xilinx System Generator for DSP Co-simulating with hardware in the loop gives you faster simulations and eases hardware verification. System Generator for DSP Version 3.1 now lets you include FPGA hardware in Simulink simulations. by Nabeel Shirazi Senior Staff Software Engineer Xilinx, Inc. nabeel.shirazi@xilinx.com Jonathan Ballagh Senior Software Engineer Xilinx, Inc. jonathan.ballagh@xilinx.com FPGA hardware can now be included in simulations controlled by the MATLAB language and its Simulink design tools. At the push of a button, the Xilinx System Generator for DSP Version 3.1 software tool produces an implementation of your model that is ready to run in hardware. System Generator uses a special cosimulation block to control the design hardware during Simulink simulations. The co-simulation block looks just like traditional System Generator blocks. Its ports have names and types that match the ports on the original System Generator subsystem. The co-simulation flow for this architecture is shown in Figure 1. The simulation behavior of the co-simulation block is bit- and cycle-accurate when compared to the behavior of the original subsystem. System Generator’s ability to incorporate hardware in the loop enables significant simulation speedups, provides incremental hardware verification capabilities, and removes many of the hurdles to getting a design up and running in an FPGA. Hardware Co-Simulation Flow Together, System Generator and hardwarein-the-loop co-simulation solve many problems normally associated with simulating and verifying a Xilinx FPGA design. • You don’t have to know a hardware description language. System Generator performs automatic code generation when your model is translated into hardware. • You don’t need in-depth knowledge of the board that hosts the FPGA. System Generator makes sure the correct hardware platform is targeted and implements the design accordingly. • You need not create a separate test bench application. The co-simulation block can be used with the same Simulink test bench apparatuses that were used to test the original System Generator model. The starting point is the System Generator model – or subsystem – that you want to co-simulate. You identify the subsystem by dragging and dropping a Figure 1 – MATLAB/Simulink and hardware co-simulation 8 Xcell Journal Fall 2003
compilation block from the XtremeDSP development kit library, for example, into the design, as shown in Figure 2. A subsystem that contains a compilation block should also contain a System Generator block. System Generator uses the compilation block to provide information about the underlying hardware Figure 2 – System Generator block and an XtremeDSP compilation block Figure 3 – System Generator dialog box with inactive product family, device, speed, and package fields and how to prepare the model for co-simulation. Pressing the “generate” button on a System Generator block that has an accompanying compilation block automatically invokes the hardware co-simulation flow. Some of the information obtained from a compilation block overrides values on the System Generator block parameters dialog box. The parameters that are overridden appear as grayed-out fields in the System Generator dialog box and cannot be modified. For example, the System Generator dialog box is shown for a subsystem that also contains an XtremeDSP compilation block. Notice in Figure 3 that the product, device, speed, and package fields have been grayed-out and are inactive. These parameters are used by System Generator when you press the “generate” button and the model is translated into hardware. This ensures that the correct device information is preserved when the FPGA configuration bit file is generated. Generating a model for hardware co-simulation includes operations such as producing HDL code and netlists and invoking the Xilinx CORE Generator tool. After System Generator has generated a model, it invokes a compilation block script. Using the output from System Generator, the compilation block script invokes the tools necessary to produce a configuration file for the FPGA. Figure 4 illustrates the XtremeDSP compilation block script running ngdbuild. The script creates a new library and adds a co-simulation block that is parameterized with information from the original subsystem. This information includes subsystem interface information such as port names, port data rates, port data types, and port directions. Figure 5 shows the library and co-simulation block created by the compilation block script for the cosim_ex model. Figure 6 shows the co-simulation block first illustrated in Figure 5 as it is brought back into the cosim_ex model for simulation. Note that the ports on the cosimulation block match the port names on the input and output gateway blocks. The waveform in the scope shows equivalent output results for the AddSub block and the co-simulation block. The block’s inputs must be the same signal type, as shown in Figure 7. Using Co-Simulation Blocks in Simulink A co-simulation block is a Simulink block that interacts with an underlying cosimulation platform. This block behaves as a normal Simulink block and can be simulated transparently with other blocks. Each co-simulation block has a port interface that is parameterized by the compilation block script to match the ports on the original subsystem. System Generator co-simulation blocks can be driven by either Xilinx fixed-point data types or by double-signal data types. The hardware co-simulation block must be of the same type of signals (bit width, binary point position, signed/unsigned) that were used in the original model. If there are no inputs to the block, the block allows you to choose between Xilinx fixedpoint or double-signal output types. Figure 4 – Compilation block script for the XtremeDSP development kit Fall 2003 Xcell Journal 9
Page 1 and 2: ISSUE 47, FALL 2003 XCELL JOURNAL X
Page 3 and 4: EDITOR IN CHIEF Carlis Collins edit
Page 5 and 6: View from the top Innovation, Educa
Page 7: High Density Spartan-3 Support ISE
Page 11 and 12: Get Physical with the PALACE Synthe
Page 13 and 14: You can control PALACE operations i
Page 15 and 16: Integration of Functions Glue Logic
Page 17 and 18: 4. Support for Xilinx V2PDK Softwar
Page 19 and 20: Resulting PAR Fmax LUT Count 135 12
Page 21 and 22: points. The ability to support many
Page 23 and 24: Get the Platform Flash PROMise Redu
Page 25 and 26: implemented. This means that there
Page 27 and 28: • Synchronizing Logic - At this s
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Page 39 and 40: nVisage captures it all As a profes
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Page 45 and 46: cisely 0-1-0-1, the cell’s fitnes
Page 47 and 48: y Liza Boland System Architect, Con
Page 49 and 50: team plans to migrate to a more com
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To give you a good jump-start on de
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User Application and Bluetooth Prot
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Support and Titanium Technical Serv
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Celoxica, IBM, Mentor Graphics, Nal
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XPERTS Partners 3T BV www.3T.nl/ De
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Mikrokrets AS www.mikrokrets.no/ FP
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XILINX CPLD http://www.xilinx.com/p
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XILINX VIRTEX-II SERIES FPGAs http:
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XILINX SPARTAN FPGAs http://www.xil
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