Discover New Applications For Low-Cost Solutions Discover ... - Xilinx
Discover New Applications For Low-Cost Solutions Discover ... - Xilinx
Discover New Applications For Low-Cost Solutions Discover ... - Xilinx
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Take the Titanium Solution<br />
<strong>Xilinx</strong> Titanium Technical Service engineers coach clients through design issues.<br />
by Vikram Pasham<br />
Design Engineer, <strong>Xilinx</strong> Design Services<br />
<strong>Xilinx</strong>, Inc.<br />
vikram.pasham@xilinx.com<br />
Need to enhance your design productivity?<br />
Decrease your design costs? Accelerate time<br />
to market? With the complexities and possibilities<br />
of today’s designs, it’s easy to get<br />
sidetracked from your main goals.<br />
<strong>Xilinx</strong> Titanium Technical Service provides<br />
on-site or off-site support for clients<br />
on a contract basis. Titanium application<br />
engineers are adept at ensuring that you<br />
start and finish your designs the right way.<br />
Our engineers provide design methodology<br />
coaching to make sure you take the most<br />
efficient approach. And our engineers’ skill<br />
at tracing debug issues back to the design is<br />
one of our most powerful services. Here’s<br />
an example from one of our clients.<br />
Customer Challenges<br />
During the development of a high-definition<br />
television (HDTV) video application, the<br />
engineering team of our client company<br />
(which prefers to remain anonymous for<br />
competitive reasons) had developed proprietary<br />
DSP algorithms for uniform video<br />
correction. These were implemented on a<br />
custom ASIC developed by a third party,<br />
which had several silicon bugs.<br />
Fearing that the bugs would cost them<br />
the chance to be first to market with their<br />
technology, the engineers ported part of the<br />
ASIC’s functionality to a <strong>Xilinx</strong> FPGA. Yet<br />
they still noticed that prototypes, when<br />
tested in the lab, had power-up and image<br />
distortion issues. Thus, they decided to<br />
bring in a dedicated <strong>Xilinx</strong> Titanium<br />
Technical Service application engineer.<br />
At the time, the customer’s main<br />
challenges were:<br />
• A densely packed design using<br />
99% slices, 70% block RAMs,<br />
and multipliers in a Virtex-II<br />
device. They wanted to add additional<br />
features into the FPGA, but did not<br />
have the budget to use a larger one.<br />
• They couldn’t meet timing in their<br />
Virtex-II –4 speed grade part and were<br />
using –5 speed grade. This increased<br />
their bill of materials.<br />
• This design had to support six different<br />
pin configurations for different RGB<br />
connectors on different boards.<br />
• The prototypes were behaving<br />
inconsistently on power-up and<br />
exhibiting image distortion.<br />
The Titanium Solution<br />
Over the course of one week, a <strong>Xilinx</strong><br />
Titanium engineer gave the client’s engineering<br />
team a crash course on FPGA<br />
design techniques and constraints. He suggested<br />
replacing the existing design’s clocking<br />
structure with Virtex-II digital clock<br />
managers (DCMs) for multiple clock generations.<br />
After learning about the features of<br />
DCMs, the engineering team discovered<br />
they could use DCM status bits to determine<br />
if the digital video interface (DVI)<br />
clock was disconnected. Based on this discovery,<br />
the team designed a robust recovery<br />
mechanism. This solved the power-up and<br />
image distortion problems.<br />
The existing design was already using all<br />
of the resources of the FPGA, yet there were<br />
further requirements to add functionality.<br />
The Titanium engineer identified portions<br />
of the design that weren’t suited for FPGA<br />
architecture. He recommended other changes<br />
for optimal efficiency, while still preserving<br />
design functionality. Knowing that Virtex-II<br />
silicon can easily meet 60 MHz DVI clock<br />
rates, he suggested using tight packing<br />
options in map tools, and using the multipass<br />
place-and-route and floorplanning features<br />
in <strong>Xilinx</strong> ISE tools. This freed up enough<br />
resources for the engineers to add the additional<br />
features in the FPGA.<br />
To meet timing in the Virtex-II –4 speed<br />
grade part for the six different pin configurations,<br />
the Titanium engineer placed timing<br />
constraints to cover all the clocks, cross clock<br />
domain paths, and multicycle paths.<br />
Together, they put together working prototypes<br />
in the lab supporting the six different<br />
pin configurations.<br />
After these adjustments to the design,<br />
the company is now able to use a lowerspeed<br />
grade part, reducing their system cost.<br />
They are on schedule to meet their time-tomarket<br />
goals.<br />
Conclusion<br />
A Titanium Technical Service application<br />
engineer can work at <strong>Xilinx</strong>, on-site, or a<br />
mix of both. This flexibility allows the<br />
engineers to fully understand the needs and<br />
requirements of our clients, as well as leverage<br />
<strong>Xilinx</strong> factory resources to resolve problems<br />
and accelerate production.<br />
<strong>For</strong> more information about Titanium<br />
Technical Services, please call 800-888-<br />
FPGA (3742) or visit http://support.<br />
xilinx.com/support/services/titanium.htm.<br />
Fall 2003 Xcell Journal 71