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In some cases the PTT button is
replaced by a voice activity detector, which
has an inherent turn-on delay, meaning that
the beginning of your transmission will
always be lost.
To eliminate loss at the beginning of
transmissions, we combined a PCM codec
with a static RAM to implement a digital
audio delay line, which holds up the voice
signal (Figure 4).
The PCM data transfers in to and out of
the codec over a high-speed 2.048 MHz
serial bus (Figure 5). Encoded PCM samples
are converted to parallel data and written
into a ring buffer in the RAM. By reading
parallel data from the RAM location with a
fixed offset (modulo the size of the ring
buffer) to the write address, the output is
delayed. The parallel data is then reconverted
and fed into the codec over a serial bus.
in
analog
out
Figure 5 – Codec to RAM
interface block diagram
Figure 4 – Digital audio delay line
One PCM sample reads/writes every 125
microseconds. The delay can be adjusted by
modifying the read-to-write address offset.
These operations, in particular the
emulation of the serial bus, cannot be performed
by a standard microprocessor,
which would be too slow. We chose a
Xilinx CoolRunner-II device with 64
macrocells for the interface between the
codec and the RAM. This solves our speed
problem and also saves PCB real estate that
would have otherwise been taken by standard
logic components.
The Development Process
Excellent support from Impact Memec,
the local Xilinx representative, kept the
development start-up time extremely
short. We used ISE WebPACK software
for all of the designs, and found it espe-
delay
D(7:0)
AD(12:0) A
codec 2.048
Mb CoolRunner-II RAM
control
cially helpful for the following reasons:
• Access to error messages on the Xilinx
website provided instant in-depth
information about the particular message,
often with hints on how to solve
the problem.
• The designs were simulated using
ModelSim XE Starter, leading to some
design modifications and allowing flaws
to be fixed early in the development
process. Some problems were due to
signal spikes on clock lines, which were
properly indicated by the simulator.
All designs loaded and operated correctly
on the first attempt when moved to
the target hardware. We have no doubt
that the design environment of the Xilinx
CoolRunner-II family of CPLDs is mature
and sound.
Conclusion
Xilinx CoolRunner-II devices are well
suited for our applications. They provide
a reliable technical solution combined
with a short development time and a low
start-up cost.
Based on this positive experience,
Girsberger Elektronik AG is planning to
incorporate Xilinx CoolRunner-II devices
in such products as:
• The upgrade and replacement of an old
avalanche beacon ASIC to eliminate
the high NRE cost.
• A beacon to locate stolen cars. By taking
over part of the training transmitter
CPLD design, we will save significant
development time.
• A data over voice interface for use on
ISDN B-channels. The CPLD beats
the speed of any microprocessor in
manipulating the bitstream on an
industry-standard IOM bus.
Although CPLDs are often associated
with high speed or high density, Xilinx
CoolRunner-II devices are an interesting
alternative for small-scale applications in
which top speed and high density are not
key concerns. For more information
about Girsberger Elektronik AG, visit
www.girsberger-elektronik.ch/.
52 Xcell Journal Fall 2003