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ics. This system implements control algorithms that accept operator inputs to point the telescope to ground-based objects of interest. • Precision optics direct the light collected by the telescope into a series of imaging cameras. Aircraft engine vibration, structural resonance, and other disturbances can wreak havoc on the alignment of these devices. To compensate for these effects, an automatic alignment system is incorporated. The goal is to stabilize the imaging system so it can yield a clear, jitter-free image for the system operators. • Sensitive imaging cameras act as the “eyes” of the electro-optical payload. These devices provide high-resolution daytime and nighttime video to real-time image processing hardware. • Sophisticated image-processing algorithms that perform video enhancement, segmentation, and feature extraction. Together, these subsystems allow an operator to identify and interrogate ground-based objects with unprecedented capability. Figure 1 highlights some of the essential functions of this system. Boeing Subsystems Boeing has chosen the Virtex-II Pro Platform as a critical element in this programmable system. The FPGA device and the supporting chips connected to it execute the following functions: • High-speed image processing • Digital-video scene generation and storage • Fiber-optic media conversion of video data • DVI display generation • NTSC video generation • Servo-control functions • High-bandwidth data transfer interfaces. Embedded DSP One reason Boeing chose the Virtex-II Pro platform is that it incorporates three of the most important elements for a modern, embedded DSP device. Aircraft Imaging System Figure 1 – Essential system functions 1. A high-performance, high-density, programmable logic fabric – this capability is the heart and soul of true parallel processing. FPGA technology lends itself very well to the repetitive, systolic nature of our algorithms. Embedded multipliers, SRL16 capabilities, true dual-port Block RAM, and a segmented routing architecture give us key enabling technologies to produce powerful designs. 2. A wealth of interface pins that can be configured for different signaling standards and easily integrated with devices from other vendors – using a single Xilinx chip, Boeing’s design team can arrange a device with a PCI bus interface, video encoder/decoder connections, digital-video display outputs, multiple SRAM interfaces, and a highspeed digital-video input port. These functions run in parallel, concurrently, without the hassles of bus contention and multi-processor scatter/gather issues. The Virtex-II Pro multi-gigabit transceivers (MGTs) raise the bar to another level. MGTs are extremely useful for the imaging camera interfaces. Boeing’s design team can use a low-end Virtex- II Pro device to serialize several parallel digital video outputs. These serial outputs are easily converted to fiber-optic media. And because the data transfer is point-to-point, designers can program the serial transceivers with a userfriendly data protocol. Optical Alignment Servo-Control Systems Image Processing 3. An embedded IBM PowerPC 405 CPU – the point of using an FPGA in many image-processing applications is to unburden the host CPU from simple, brute-force calculations. With the embedded PowerPC CPU, the host is left unimpeded to handle the complex decision-making logic that forms the brains of a system. PowerPC Advantages Many people might argue that it’s easy enough to hook an FPGA to a PCI bus interface – so why bother with the embedded PowerPC CPU in the Virtex-II Pro platform? For some applications, a PCI interface is sufficient, but Boeing’s design team has found many compelling reasons to choose an embedded CPU: • By using logic to accelerate the embedded CPU, most of the residual backend processing for our applications requires only a modest amount of compute power. We all like having multi-GHz CPU power, but it is not always necessary. • The embedded PowerPC CPU consumes a fraction of the power of a highend CPU, while remaining directly coupled to the logic fabric. In Boeing’s business, it seems that Moore’s law does not always apply. RISC CPUs for embedded applications have not generally kept pace with desktop systems in terms of clock speed and performance. Packaging and thermal dissipation con- 54 Xcell Journal Summer 2003
straints make it very hard for embedded hardware developers to offer multi-GHz-class processor subsystems in a small form factor. DSP processors address many power consumption issues, but lack the logic interface flexibility. For many applications, the embedded PowerPC provides the right balance of performance, power, interface, and general-purpose computing capability. • Those who think PCI is easy should try using the CoreConnect bus with dual-port RAMs. In a matter of minutes, you can configure an FPGA interface to a 405 processor via highspeed BRAM. It’s like having your data put right into the cache RAM. Now consider that multiple, independent FPGA processes can stuff these RAMs in parallel – and with completely different clocks than those used by the PowerPC CPU. You get high-bandwidth, extremely simple data transfer without the vices or overhead of PCI. Put simply, there is far more room for creative interfaces, application-specific tailoring, and flexibility in the Virtex-II Pro platform. • Consider your application model for your microprocessor. Boeing’s design team gets plenty of mileage out of using the embedded CPU as a “microcontroller.” If you dispose of a fullblown operating system and run the PowerPC CPU with a lightweight kernel, the internal Block RAM can hold a significant amount of user code. Even better, the FPGA is now both hardware and software reconfigurable – in real time. A single unified bitstream defines the operating characteristics for both the CPU and logic. Major Features In addition to the device’s embedded DSP capability, Boeing’s design team makes use of almost every major feature of the Virtex-II Pro logic fabric: • The embedded multipliers are very useful for DSP-based algorithms. They provide high silicon efficiency and effortlessly support the clock rates our designs require. Legacy Approach: 3.5"x14"x14" M CH9 7 5 0 R I N J R I N J Fiber Optic Link 7 7 5 5 0 0 M 7 M CH9 7 5 CH9 5 0 0 R I 7N 5J 0 R I N J 7 5R 0 I 7N 5J 0 R I N J 7 5 0 7 5 0 7 5 0 • The dual-port Block RAM is a veritable Swiss Army knife in terms of functionality. It can be used for tapped delay lines, command and status data buffers, lookup tables, bus-width conversion, FIFOs, and so forth. • The SRL16 capability with dedicated fast-carry logic gives the Virtex-II Pro platform a key advantage in DSP applications. Both features are critical to the design of high-performance digital filters and the SRL16 mode helps to significantly reduce the logic footprint of DSP algorithms. • DCI (digitally controlled impedance) technology is a significant aid when implementing functions such as DDR RAM interfaces. Boeing’s PCB designer no longer struggles with finding a way to place hundreds of termination resistors. • The DCMs (digital clock managers) provide an easy-to-use, flexible clock management scheme. Our design team has leveraged both the frequency synthesis and precision phase shifting capabilities in many designs. The new ISE architecture wizards make instantiating them easy. • The MGTs allow us to create highbandwidth interfaces to a high-speed serial link that operates as if it were a parallel data bus. Ninety-five percent of the design problems in this application are simply about sending pixel data from A to B. Rapid IO, 3GIO, InfiniBand, or Fibre Channel are generally overkill for this type of data transfer requirement. The MGTs provide serial interfaces in a way that has reduced board size tremendously. The 8b/10b and SerDes (serializer/deserializer) chips that we used in a prior design were actually bigger than an entire Virtex-II Pro device. Figure 2 shows how the Virtex-II Pro platform enabled Boeing’s design team to dramatically reduce system size and cost. Boeing’s high-performance imaging system is taking advantage of the complete Xilinx solution. We are using most of the features in the silicon as well as Xilinx handcrafted IP cores, System Generator for DSP, and CORE Generator tools. These tools enable us to focus on the specific elements of the design and spend less time constructing the architecture that surrounds it. Conclusion Virtex-II Pro Platform FPGAs raise the bar of both capability and complexity for programmable system design. Boeing’s design team chose Xilinx solutions because the Virtex-II Pro Platform FPGA offers unmatched “system” capability along with a broad range of devices from which to choose. For more information on Virtex-II Pro Platform FPGAs and design resources, go to www.xilinx.com/virtex2pro. Summer 2003 Xcell Journal 55 7 5 0 (x8) (x16) PowerPC Processors Figure 2 – Before and after Virtex-II Pro implementation New Approach: 3.5"x7"x1" Four 9U VME Boards Additional Bootstrap Host Separate Image Display Card Cost: $250-500 K Weight: ~14 lbs Power: ~300 Watts DSP Capability: < 32 Billion MACs/s S/W Programmable M ART Virtex-II Pro FPGA (x1) Parallel Optical Link (x1) PowerPC (x1) One 3U Compact PCI Card Integrated DVI Display Chip Cost: < $15K Weight: < 1 lb Power: ~25 Watts DSP Capability: 100 Billion Macs/s Real-Time Reconfigurable
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ISSUE 47, FALL 2003 XCELL JOURNAL X
Page 3 and 4: EDITOR IN CHIEF Carlis Collins edit
Page 5 and 6: View from the top Innovation, Educa
Page 7 and 8: High Density Spartan-3 Support ISE
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Page 11 and 12: Get Physical with the PALACE Synthe
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Page 15 and 16: Integration of Functions Glue Logic
Page 17 and 18: 4. Support for Xilinx V2PDK Softwar
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Page 21 and 22: points. The ability to support many
Page 23 and 24: Get the Platform Flash PROMise Redu
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Page 27 and 28: • Synchronizing Logic - At this s
Page 29 and 30: 64 Light Sensors LOAD Although this
Page 31 and 32: The DQS net could potentially be de
Page 33 and 34: Design Security Consider the philos
Page 35 and 36: Bitstream Encryption Simple Encrypt
Page 37 and 38: System Challenges The differing req
Page 39 and 40: nVisage captures it all As a profes
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Page 45 and 46: cisely 0-1-0-1, the cell’s fitnes
Page 47 and 48: y Liza Boland System Architect, Con
Page 49 and 50: team plans to migrate to a more com
Page 51 and 52: ands on the market. We use a 73.768
Page 53: Boeing Harnesses Virtex-II Pro Plat
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Page 59 and 60: To give you a good jump-start on de
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Page 63 and 64: • Two HSSDC2 connectors for imple
Page 65 and 66: y Jim Beneke Director of Technical
Page 67 and 68: User Application and Bluetooth Prot
Page 69 and 70: from one fabrication line to anothe
Page 71 and 72: Take the Titanium Solution Xilinx T
Page 73 and 74: Support and Titanium Technical Serv
Page 75: Celoxica, IBM, Mentor Graphics, Nal
Page 78 and 79: Xilinx AllianceCORE Third-Party IP
Page 80 and 81: XPERTS Partners 3T BV www.3T.nl/ De
Page 82 and 83: Mikrokrets AS www.mikrokrets.no/ FP
Page 85 and 86: XILINX CPLD http://www.xilinx.com/p
Page 87 and 88: XILINX VIRTEX-II SERIES FPGAs http:
Page 89 and 90: XILINX SPARTAN FPGAs http://www.xil
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Page 99 and 100: Avoid messy timing mistakes. Use Me
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