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Integration of Functions
Glue Logic
Gates
Distributed Memory
System-Level
Function Blocks
Block RAM
High-Speed I/O
Multipliers
DCM
1980s 1990s 2000s
Figure 1 – Paradigm shift in programmable platforms
critical part of the overall debug process. It
is therefore important that specialized tools
and methodologies be developed that promote
debug efficiency and provide a
streamlined approach to verification.
For a while now, HW/SW co-verification
has been quite commonly used to
debug ASIC SoC designs. Now, with an
increasing number of FPGA design starts
involving embedded processors, this technology
is becoming meaningful and important
for FPGA designers as well.
Co-Verification for Platform FPGAs
Mentor Graphics’ Seamless Co-
Verification Environment (CVE) is the
industry’s leading HW/SW co-verification
tool – and now it supports the Xilinx
Virtex-II Pro family of FPGAs. The
basic concept behind co-verification is to
merge the respective debug environments
used by hardware and software teams into a
single framework.
For example, a logic simulator is made to
communicate with a software debugger,
enabling you to get simultaneous control
and visibility into the internals of the processor,
as well as the hardware peripheral logic
that surrounds it, as shown in Figure 2.
An efficient co-verification tool can help
uncover a range of HW/SW interface
problems, including:
• Initial startup and boot sequence errors
(including RTOS boot)
• Processor and peripheral initialization
and configuration problems
Platform for
Programmable
Systems
Platform FPGAs
• Memory accessing and initialization
problems
• Memory map and register map
discrepancies
• Interrupt service routine errors.
To realize the many benefits that coverification
has to offer, there are three
prerequisites for the design under test. A
co-verification design environment typically
involves the following scenario:
1. The system has a processor executing
software code that interacts with surrounding
custom peripheral logic.
2. There is extensive interaction between
software and hardware parts of the
design during execution.
3. Both hardware and software engineering
teams agree on using co-simulation
early in the design stage.
Software
Debugger
PPC
405
ISS
SW Domain
10,000X Faster Access to Memory
These prerequisites guarantee a smooth
methodology flow and a common communication
medium between the two teams.
Co-Verification vs. Simulation
Seamless CVE advances the concept of
“functional simulation” in traditional logiconly
FPGA designs to “co-verification” in
processor-based Virtex-II Pro Platform
FPGAs. This methodology establishes value
for multiple design teams including hardware
engineers (peripheral logic debug),
embedded software engineers (application
and firmware debug), and system designers
(performance analysis and tuning). Let’s discuss
some of the many advantages Seamless
co-verification offers over simulation.
Faster Performance
Pure logic simulation can be used to simulate
a design with a processor component. This is
accomplished by including an RTL model of
the processor to simulate the software code.
This approach, however, is painfully
slow and not adequate to address all but
the most basic debug requirements. The
overall simulation speed is generally in the
sub-100 Hz range.
Co-verification, on the other hand, is
able to run simulation orders of magnitude
faster. This speedup is achieved primarily
through the use of clever tool optimizations
and faster processor models known as
instruction set simulators (ISSs).
To understand the concept of optimization,
note that the real bottlenecks in simulation
are due to the accurate but slow logic
simulators. Every time the software needs to
CoreConnect
Bus Model
On-Chip
Off-Chip
Memories
HW Domain
Peripherals
Fall 2003 Xcell Journal 15
CVE
Kernel
Memory
Server
BIM
A
D
A
D
Logic
Simulator
Figure 2 – The Seamless Co-Verification Environment connects hardware and software verification
environments for Virtex-II Pro FPGAs.