Discover New Applications For Low-Cost Solutions Discover ... - Xilinx
Discover New Applications For Low-Cost Solutions Discover ... - Xilinx
Discover New Applications For Low-Cost Solutions Discover ... - Xilinx
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<strong>Xilinx</strong> Alliance EDA<br />
Members and Products<br />
Alatek<br />
www.alatek.com<br />
Hardware acceleration (HES)<br />
Altium<br />
www.altium.com/products/nvisage.htm<br />
Complete PCB/FPGA design flow<br />
(nVisage) targeting Spartan Series FPGAs<br />
Apache Design<br />
www.apache-da.com/Products/nspice.htm<br />
HSPICE ® -compatible simulator using<br />
actual S-parameter data (NSPICE) for<br />
Virtex-II Pro MGT-based PCB design<br />
Aplus<br />
www.aplus.com<br />
Architecture-specific synthesis and layout<br />
optimization for Virtex-II series FPGA<br />
(PALACE)<br />
Aptix<br />
www.aptix.com<br />
ASIC emulation (Prototype Studio)<br />
Atrenta<br />
www.atrenta.com<br />
RTL Linter technology for Virtex-II series<br />
FPGAs (SpyGlass ® )<br />
Cadence Design Systems<br />
www.cadence.com/feature/fpga_design.html<br />
Virtex-II Pro MGT support for high-speed<br />
PCB design (SPECCTRAQuest ® ); NCSim<br />
family for FPGA design simulation; SPW<br />
for DSP data path development on FPGAs<br />
Celoxica<br />
www.celoxica.com<br />
C-level design creation, compilation, and<br />
verification for Virtex-II and Virtex-II Pro<br />
FPGAs<br />
Endeavor<br />
www.endeav.com<br />
Co-verification for Virtex-II Pro<br />
(CoSimple)<br />
EVE<br />
www.eve-team.com<br />
RTL-level Simulator Accelerator (ZEBU)<br />
<strong>For</strong>te Design<br />
www.forteds.com<br />
HLL compiler to RTL (Cynlib Tool Suite);<br />
timing specification and analysis tool<br />
(TimingDesigner)<br />
Future Design Automation<br />
www.future-da.com<br />
ANSI-C algorithms to RTL models<br />
(SystemCenter)<br />
Hierarchical Design Inc. (HDI)<br />
www.hierdesign.com<br />
Hierarchical floorplanning and analysis<br />
software for Virtex-II series FPGAs<br />
Mentor Graphics<br />
www.mentor.com<br />
Virtex-II Pro MGT support for high-speed<br />
PCB design (HyperLynx, ICX,<br />
Tau); complete FPGA design flow using<br />
the ModelSim ® family of simulators and<br />
Leonardo-Spectrum/Precision ® synthesis;<br />
Seamless ® co-verification support for<br />
Virtex-II Pro<br />
Novilit<br />
www.novilit.com<br />
Design partitioning using ISE EDK<br />
(AnyWare) for Virtex-II series FPGAs<br />
Product Acceleration Inc.<br />
www.prodacc.com<br />
FPGA symbol generation<br />
(LiveComponent); automated pin<br />
assignment optimization; PCB layer count<br />
control (DesignF/X)<br />
Simucad<br />
www.simucad.com<br />
Verilog simulator for FPGAs (Silos)<br />
Synopsys<br />
www.synopsys.com<br />
Virtex-II Pro multigigabit transceiver<br />
support for high-speed PCB design<br />
(HSPICE ® ); FPGA Compiler II RTL<br />
synthesis for Virtex series FPGAs;<br />
VCS(MX)/Scirocco(MX) simulators;<br />
<strong>For</strong>mality ® formal verification, LEDA ®<br />
RTL linter, and PrimeTime static<br />
timing analysis; high-level design using<br />
CoCentric System C Compiler and<br />
CoCentric System Studio<br />
Synplicity<br />
www.synplicity.com<br />
RTL synthesis (Synplify ® ), debugger<br />
technology (Identify ® ), and physical<br />
synthesis (Amplify ® ) for all <strong>Xilinx</strong> FPGAs<br />
Translogic<br />
www.translogiccorp.com<br />
FPGA symbol generation for fast PCB<br />
design iterations (FPGA Connector)<br />
for Virtex-II series FPGAs<br />
Verplex<br />
www.verplex.com<br />
<strong>For</strong>mal verification technology for Virtex-II<br />
series FPGAs (Conformal LEC)<br />
Fall 2003 Xcell Journal 77
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