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System Challenges
The differing requirements of 3G backhaul
and residential/SME applications mean
that, as a designer, you must create access
solutions that are capable of handling a
wide range of services. These include legacy
services such as time division multiplexing
(TDM), IP (Internet Protocol), and VoIP
(Voice over Internet Protocol). A variety of
backhaul requirements must also be accommodated,
including ATM and packet-based
protocols. In other words, your design must
have enough flexibility to efficiently carry
any traffic type.
Maintaining QoS and delivering
99.999% availability, or “five
9s,” is made more difficult by
environmental effects such as
rain, obstructions, or other nonline-of-sight
conditions. Both
the IEEE and ETSI standards
have introduced adaptive coding
and modulation algorithms that
make the best use of the available
bandwidth under favorable link
conditions, and they invoke a
more reliable alternative to maintain
availability under unfavorable
link conditions. Co-channel
interference also acts to degrade
link quality, and both standards
address this issue as well.
A wireless access system may
be presented with multiple connections
per terminal, multiple QoS levels
per terminal, and a large number of statistically
multiplexed users. As a result, secondgeneration
systems demand an extremely
high-performance, scalable, signal processing
platform designed for wireless processing
and dataflow.
Physical Layer Design
While the Media Access Control (MAC)
layer handles algorithms relevant to the
various traffic classes, complex adaptive
coding and modulation are performed at
the PHY (physical) layer.
The PHY specifications for IEEE
802.16 and ETSI BRAN standards establish
a burst specification that allows both
time-division duplexing (TDD) and
frequency-division duplexing (FDD). Both
TDD and FDD support adaptive burst
profiles in which transmission parameters
relevant to modulation and coding may be
assigned dynamically on a burst-by-burst
basis. Further complexity is added by
including support for half-duplex FDD
subscriber stations (which may help to
reduce the cost of subscriber equipment
because they do not simultaneously transmit
and receive).
Variable burst profiles require extensive
processing resources, including Reed-
Solomon forward error correction (FEC)
with variable block size and error correc-
tion capabilities. Moreover, FEC is combined
with 16-state quadrature amplitude
modulation (16-QAM) or 64-QAM in
both ETSI BRAN and IEEE 802.16. ETSI
BRAN also defines 4-QAM.
A PHY implementation for either standard
integrates transceiver and CODEC
(coder/decoder) functions as well as backplane
interfaces and data queuing. This
implementation calls for complex mixers,
frequency synthesizers, mapping capability,
automatic gain control, and access
point synchronization in the transceiver.
Additional CODEC blocks include:
Viterbi and convolutional coding; interface
buffering; PDU header controls and
scramble/descramble; and MUX/DEMUX
(multiplexer/demultiplexer) functions.
Additional interfacing and data-queuing
functions include frame formatting, cell
queuing, and lookup or PDU overhead
formatting.
As a result, ETSI- or IEEE-compliant
base stations must integrate extensive processing
capabilities, many of which you can
perform in hardware.
Hardware Acceleration
In both second-generation BFWA standards,
the algorithmic complexity of the
PHY layer in particular has accelerated
faster than Moore’s law can empower DSPs
to keep pace. Still, a software-reconfigurable
solution is desirable given the
current uncertain market conditions.
Market projections are
under constant review, and
some manufacturers believe
further harmonization of standards
must take place before
the true potential of BFWA will
be realized.
All of these factors make it
extremely difficult to plan an
ASIC development with confidence.
These factors also make
creating the ICs for standardscompliant
equipment a significant
challenge, especially if you
want to avoid the fixed engineering
development costs.
On the other hand, highspeed
FPGAs allow you to
create custom hardware and exploit the
massive parallelism needed to meet performance
goals without sacrificing flexibility.
You can also achieve high
integration by implementing DSP functions
alongside protocol translation, glue
logic, and other system functions. The
Virtex-II and Spartan FPGA families
also provide a wealth of processing
resources, including Xilinx MicroBlaze
soft processor cores, as many as four
embedded IBM PowerPC cores (in
Virtex-II Pro Platform FPGAs), and
user-selectable I/Os.
These resources combine well with large
IP (intellectual property) libraries, through
which Xilinx offers functions such as
Viterbi, turbo-product coding, and other
off-the-shelf functions.
Fall 2003 Xcell Journal 37