Discover New Applications For Low-Cost Solutions Discover ... - Xilinx

8-bit microcontroller interface, take a look
at application note XAPP349.
Memory Interface
The CoolRunner-II design board may well
be the best solution for testing new memory
interfaces. With multiple memory interfaces
– including HSTL, SSTL, and
LVCMOS – you can test SDRAM,
SSDRAM, MSDRAM (mobile SDRAM),
UtRAM (UniTransistor RAM), cellular
RAM, and flash memories. You can even
design your own memory controller for
new flavors of portable or mobile RAM as
they become available.
The CPLD application notes webpage
contains many memory design examples,
including beginning designs for flash and
DDR SDRAM memory. Check this website
often for new memory interfaces and
updates or to download an HDL design
and get email notification of new application
notes.
Crosspoint Switch
The non-blocking architecture allows each
output to be independently connected to
any input, and any input to be connected to
any or all outputs. The double-row latch
architecture utilized in this design allows
switch reprogramming to occur in the background
during operation. Activation of the
new configuration occurs with a single configuration
pulse. Each output can be individually
disabled and set to a high-impedance
state, allowing easy expansion to larger
switch array sizes. This is covered in detail in
application note XAPP380.
OTF Reconfiguration
On the fly (OTF) reconfiguration permits
the CPLD to operate with an initial design
pattern while simultaneously acquiring a
second pattern. For example, your first
design pattern can be a power-up application,
such as a built-in self-test (BIST), and
the second pattern can be one of normal
device operation. If you want to run diagnostics
on your system on power-up, you
would load a functional pattern to perform
additional bus interface support. The second
pattern can be configured into the device
with minimal disturbance to its operation.
Another important consideration is that
OTF reconfiguration enhances security,
because switching keys on the fly permits
robust protocols for data communication
designs that can be tough to crack. OTF
reconfiguration takes in-system programming
(ISP) to a new level and will
undoubtedly spawn many new applications
that take advantage of this capability. More
information about OTF can be found in
application note XAPP388.
FPGA Downloader
Another common use for CPLDs is as an
FPGA downloader. At power-up the CPLD
sequentially loads each FPGA with a pattern,
which is stored in exter-
nal memory. By assigning a
CPLD to accomplish this
task, you can get double duty
from the CPLD. On powerup,
it loads the FPGA; after
this power-up task is done,
you can OTF reconfigure the
CPLD and use it as a functioning
device in your
design. It’s like getting two
devices for the price of one.
To learn more about this
application, see application
note XAPP137.
XAPP137
If you do experience problems, a website
has been set up for you at www.
digilentinc.com to help troubleshoot the board.
Conclusion
CoolRunner-II RealDigital CPLDs can be
the perfect solution for any highspeed/low-power
design and cover many
application areas. In addition to their features,
these devices also come in packages
that suit high volume and small form factor
packaging.
To order your CoolRunner-II RealDigital
Design Kit, just go to www.xilinx.com/cpld/
and click on “CoolRunner-II Design Kit
for $49.99.”
Configuring Virtex FPGAs from Parallel EPROMs
with a CPLD
XAPP345 IrDA and UART Design in a CoolRunner CPLD
XAPP346 Low Power Tips for CoolRunner Design
XAPP349 CoolRunner CPLD 8051 Microcontroller Interface
XAPP380 Building Crosspoint Switches with CoolRunner-II CPLDs
XAPP387 PicoBlaze 8-Bit Microcontroller for CPLD Devices
XAPP388 “On the Fly” Reconfigurations
Table 1 – All CoolRunner-II application notes can be
found at www.xilinx.com/apps/epld.htm.
60 Xcell Journal Fall 2003