VS1033 - MP3/AAC/WMA/MIDI AUDIO CODEC - VLSI Solution

VLSISolution yVS1033cVS1033C7. SPI BUSEStXCSStWLtWHtXCSHXCS0 1 14 15 1630 31tXCSSCKSISOtZtHtSUtVtDISFigure 9: SPI Timing Diagram.7.6 SPI Timing DiagramSymbol Min Max UnittXCSS 5 nstSU 0 nstH 2 CLKI cyclestZ 0 nstWL 2 CLKI cyclestWH 2 CLKI cyclestV 2 (+25 ns 1 ) CLKI cyclestXCSH 1 CLKI cyclestXCS 2 CLKI cyclestDIS 10 ns1 25ns is when pin loaded with 100pF capacitance. The time is shorter with lower capacitance.Note: Although the timing is derived from the internal clock CLKI, the system always starts up in 1.0×mode, thus CLKI=XTALI. After you have configured a higher clock through SCI CLOCKF and waitedfor DREQ to rise, you can use a higher SPI speed as well.Note: Because tWL + tWH + tH is 6×CLKI + 25 ns, the maximum speed for SCI reads is CLKI/7.Version 1.00, 2008-02-01 22