VS1033 - MP3/AAC/WMA/MIDI AUDIO CODEC - VLSI Solution

VLSISolution yVS1033cVS1033C8. FUNCTIONAL DESCRIPTION8.6 Serial Control Interface (SCI)The serial control interface is compatible with the SPI bus specification. Data transfers are always 16bits. VS1033 is controlled by writing and reading the registers of the interface.The main controls of the control interface are:• control of the operation mode, clock, and builtin effects• access to status information and header data• access to encoded digital data• uploading user programs8.7 SCI RegistersVS1033 sets DREQ low when it detects an SCI operation and restores it when it has processed theoperation. The duration depends on the operation. If DREQ is low when an SCI operation is performed,it also stays low after SCI operation processing.If DREQ is high before a SCI operation, do not start a new SCI/SDI operation before DREQ is highagain. If DREQ is low before a SCI operation because the SDI can not accept more data, make certainthere is enough time to complete the operation before sending another.SCI registers, prefix SCIReg Type Reset Time 1 Abbrev[bits] Description0x0 rw 0x800 70 CLKI 4 MODE Mode control0x1 rw 0x0C 3 40 CLKI STATUS Status of VS10330x2 rw 0 2100 CLKI BASS Built-in bass/treble enhancer0x3 rw 0 11000 XTALI 5 CLOCKF Clock freq + multiplier0x4 rw 0 40 CLKI DECODE TIME Decode time in seconds0x5 rw 0 3200 CLKI AUDATA Misc. audio data0x6 rw 0 80 CLKI WRAM RAM write/read0x7 rw 0 80 CLKI WRAMADDR Base address for RAM write/read0x8 r 0 - HDAT0 Stream header data 00x9 r 0 - HDAT1 Stream header data 10xA rw 0 3200 CLKI 2 AIADDR Start address of application0xB rw 0 2100 CLKI VOL Volume control0xC rw 0 50 CLKI 2 AICTRL0 Application control register 00xD rw 0 50 CLKI 2 AICTRL1 Application control register 10xE rw 0 50 CLKI 2 AICTRL2 Application control register 20xF rw 0 50 CLKI 2 AICTRL3 Application control register 31 This is the worst-case time that DREQ stays low after writing to this register. The user may choose toskip the DREQ check for those register writes that take less than 100 clock cycles to execute.2 In addition, the cycles spent in the user application routine must be counted.3 Firmware changes the value of this register immediately to 0x58, and in less than 100 ms to 0x50.4 When mode register write specifies a software reset the worst-case time is 20000 XTALI cycles.5 Writing to this register may force internal clock to run at 1.0 × XTALI for a while. Thus it is not agood idea to send SCI or SDI bits while this register update is in progress.Version 1.00, 2008-02-01 35