VS1033 - MP3/AAC/WMA/MIDI AUDIO CODEC - VLSI Solution

More documents

Recommendations

Info

VLSISolution yVS1033cVS1033C10. VS1033 REGISTERS10.12 Timers v1.0 2002-04-23There are two 32-bit timers that can be initialized and enabled independently of each other. If enabled,a timer initializes to its start value, written by a processor, and starts decrementing every clock cycle.When the value goes past zero, an interrupt is sent, and the timer initializes to the value in its start valueregister, and continues downcounting. A timer stays in that loop as long as it is enabled.A timer has a 32-bit timer register for down counting and a 32-bit TIMER1 LH register for holding thetimer start value written by the processor. Timers have also a 2-bit TIMER ENA register. Each timer isenabled (1) or disabled (0) by a corresponding bit of the enable register.10.12.1 RegistersTimer registers, prefix TIMERReg Type Reset Abbrev Description0xC030 r/w 0 CONFIG[7:0] Timer configuration0xC031 r/w 0 ENABLE[1:0] Timer enable0xC034 r/w 0 T0L Timer0 startvalue - LSBs0xC035 r/w 0 T0H Timer0 startvalue - MSBs0xC036 r/w 0 T0CNTL Timer0 counter - LSBs0xC037 r/w 0 T0CNTH Timer0 counter - MSBs0xC038 r/w 0 T1L Timer1 startvalue - LSBs0xC039 r/w 0 T1H Timer1 startvalue - MSBs0xC03A r/w 0 T1CNTL Timer1 counter - LSBs0xC03B r/w 0 T1CNTH Timer1 counter - MSBs10.12.2 Configuration TIMER CONFIGTIMER CONFIG BitsName Bits DescriptionTIMER CF CLKDIV 7:0 Master clock dividerTIMER CF CLKDIV is the master clock divider for all timer clocks. The generated internal clockfrequency f i = fmc+1 , where f m is the master clock frequency and c is TIMER CF CLKDIV. Example:With a 12 MHz master clock, TIMER CF DIV=3 divides the master clock by 4, and the output/samplingclock would thus be f i = 12MHz3+1= 3MHz.Version 1.00, 2008-02-01 68
VLSISolution yVS1033cVS1033C10. VS1033 REGISTERS10.12.3 Configuration TIMER ENABLETIMER ENABLE BitsName Bits DescriptionTIMER EN T1 1 Enable timer 1TIMER EN T0 0 Enable timer 010.12.4 Timer X Startvalue TIMER Tx[L/H]The 32-bit start value TIMER Tx[L/H] sets the initial counter value when the timer is reset. The timerinterrupt frequency f t =f ic+1 where f i is the master clock obtained with the clock divider (see Chapter10.12.2 and c is TIMER Tx[L/H].Example: With a 12 MHz master clock and with TIMER CF CLKDIV=3, the master clock f i = 3MHz.If TIMER TH=0, TIMER TL=99, then the timer interrupt frequency f t = 3MHz99+1 = 30kHz.10.12.5 Timer X Counter TIMER TxCNT[L/H]TIMER TxCNT[L/H] contains the current counter values. By reading this register pair, the user may getknowledge of how long it will take before the next timer interrupt. Also, by writing to this register, aone-shot different length timer interrupt delay may be realized.10.12.6 InterruptsEach timer has its own interrupt, which is asserted when the timer counter underflows.Version 1.00, 2008-02-01 69
Page 2 and 3:
VLSISolution yVS1033cVS1033CCONTENT
Page 5 and 6:
Page 7 and 8:
Page 9 and 10:
VLSISolution yVS1033cVS1033C1. LICE
Page 11 and 12:
VLSISolution yVS1033cVS1033C4. CHAR
Page 13 and 14:
1.10 REFVLSISolution yVS1033cVS1033
Page 15 and 16:
VLSISolution yVS1033cVS1033C5. PACK
Page 17 and 18: VLSISolution yVS1033cVS1033C7. SPI
Page 25 and 26: VLSISolution yVS1033cVS1033C8. FUNC
Page 45 and 46: VLSISolution yVS1033cVS1033C9. OPER
Page 59 and 60: VLSISolution yVS1033cVS1033C10. VS1
Page 67: VLSISolution yVS1033cVS1033C10. VS1
Page 75 and 76: VLSISolution yVS1033cVS1033C11. DOC
show all

VS1033 - MP3/AAC/WMA/MIDI AUDIO CODEC - VLSI Solution

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?