VS1033 - MP3/AAC/WMA/MIDI AUDIO CODEC - VLSI Solution

VLSISolution yVS1033cVS1033C10. VS1033 REGISTERS10.11.3 Data UARTx DATAA read from UARTx DATA returns the received byte in bits 7:0, bits 15:8 are returned as ’0’. If there isno more data to be read, the receiver data register full indicator will be cleared.A receive interrupt will be generated when a byte is moved from the receiver shift register to the receiverdata register.A write to UARTx DATA sets a byte for transmission. The data is taken from bits 7:0, other bits in thewritten value are ignored. If the transmitter is idle, the byte is immediately moved to the transmitter shiftregister, a transmit interrupt request is generated, and transmission is started. If the transmitter is busy,the UART ST TXFULL will be set and the byte remains in the transmitter data register until the previousbyte has been sent and transmission can proceed.10.11.4 Data High UARTx DATAHThe same as UARTx DATA, except that bits 15:8 are used.10.11.5 Divider UARTx DIVUARTx DIV BitsName Bits DescriptionUART DIV D1 15:8 Divider 1 (0..255)UART DIV D2 7:0 Divider 2 (6..255)The divider is set to 0x0000 in reset. The ROM boot code must initialize it correctly depending on themaster clock frequency to get the correct bit speed. The second divider (D 2 ) must be from 6 to 255.The communication speed f =TX/RX speed in bps.f m(D 1 +1)×(D 2 ) , where f m is the master clock frequency, and f is theDivider values for common communication speeds at 26 MHz master clock:Example UART Speeds, f m = 26MHzComm. Speed [bps] UART DIV D1 UART DIV D24800 85 639600 42 6314400 42 4219200 51 2628800 42 2138400 25 2657600 1 226115200 0 226Version 1.00, 2008-02-01 66