VS1033 - MP3/AAC/WMA/MIDI AUDIO CODEC - VLSI Solution

VLSISolution yVS1033cVS1033C9. OPERATION9 Operation9.1 ClockingVS1033 operates on a single, nominally 12.288 MHz fundamental frequency master clock. This clockcan be generated by external circuitry (connected to pin XTALI) or by the internal clock crystal interface(pins XTALI and XTALO).VS1033 can also use 24..26 MHz clocks when SM CLK RANGE is set to 1. From the chip’s point ofview the input clock is then 12..13 MHz.9.2 Hardware ResetWhen the XRESET -signal is driven low, VS1033 is reset and all the control registers and internal statesare set to the initial values. XRESET-signal is asynchronous to any external clock. The reset modedoubles as a full-powerdown mode, where both digital and analog parts of VS1033 are in minimumpower consumption stage, and where clocks are stopped. Also XTALO is grounded.When XRESET is asseted, all output pins go to their default states. All input pins will go to highimpedancestate (to input state), except SO, which is still controlled by the XCS.After a hardware reset (or at power-up) DREQ will stay down for around 20000 clock cycles, whichmeans an approximate 1.6 ms delay if VS1033 is run at 12.288 MHz. After this the user should setsuch basic software registers as SCI MODE, SCI BASS, SCI CLOCKF, and SCI VOL before startingdecoding. See section 8.7 for details.If the input clock is 24..26 MHz, SM CLK RANGE should be set as soon as possible after a chip resetwithout waiting for DREQ.Internal clock can be multiplied with a PLL. Supported multipliers through the SCI CLOCKF registerare 1.0 × . . . 4.5× the input clock. Reset value for Internal Clock Multiplier is 1.0×. If typical valuesare wanted, the Internal Clock Multiplier needs to be set to 3.0× after reset. Wait until DREQ rises, thenwrite value 0x9800 to SCI CLOCKF (register 3). See section 8.7.4 for details.Version 1.00, 2008-02-01 44