VS1033 - MP3/AAC/WMA/MIDI AUDIO CODEC - VLSI Solution

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VLSISolution yVS1033cVS1033C9. OPERATION9.10.3 Memory TestMemory test mode is initialized with the 8-byte sequence 0x4D 0xEA 0x6D 0x54 0 0 0 0. After thissequence, wait for 500000 clock cycles. The result can be read from the SCI register SCI HDAT0, and’one’ bits are interpreted as follows:Bit(s) Mask Meaning15 0x8000 Test finished14:7 Unused6 0x0040 Mux test succeeded5 0x0020 Good I RAM4 0x0010 Good Y RAM3 0x0008 Good X RAM2 0x0004 Good I ROM1 0x0002 Good Y ROM0 0x0001 Good X ROM0x807fAll okMemory tests overwrite the current contents of the RAM memories.9.10.4 SCI TestSci test is initialized with the 8-byte sequence 0x53 0x70 0xEE n 0 0 0 0, where n − 48 is the registernumber to test. The content of the given register is read and copied to SCI HDAT0. If the register to betested is HDAT0, the result is copied to SCI HDAT1.Example: if n is 48, contents of SCI register 0 (SCI MODE) is copied to SCI HDAT0.Version 1.00, 2008-02-01 58
VLSISolution yVS1033cVS1033C10. VS1033 REGISTERS10 VS1033 Registers10.1 Who Needs to Read This ChapterUser software is required when a user wishes to add some own functionality like DSP effects to VS1033.However, most users of VS1033 don’t need to worry about writing their own code, or about this chapter,including those who only download software plug-ins from VLSI Solution’s Web site.10.2 The Processor CoreVS DSP is a 16/32-bit DSP processor core that also had extensive all-purpose processor features. VLSISolution’s free VSKIT Software Package contains all the tools and documentation needed to write, simulateand debug Assembly Language or Extended ANSI C programs for the VS DSP processor core.VLSI Solution also offers a full Integrated Development Environment VSIDE for full debug capabilities.10.3 VS1033 Memory MapVS1033’s Memory Map is shown in Figure 16.10.4 SCI RegistersSCI registers described in Chapter 8.7 can be found here between 0xC000..0xC00F. In addition to theseregisters, there is one in address 0xC010, called SCI CHANGE.SCI registers, prefix SCIReg Type Reset Abbrev[bits] Description0xC010 r 0 CHANGE[5:0] Last SCI access addressSCI CHANGE bitsName Bits DescriptionSCI CH WRITE 4 1 if last access was a write cycleSCI CH ADDR 3:0 SCI address of last access10.5 Serial Data RegistersSDI registers, prefix SERReg Type Reset Abbrev[bits] Description0xC011 r 0 DATA Last received 2 bytes, big-endian0xC012 w 0 DREQ[0] DREQ pin controlVersion 1.00, 2008-02-01 59
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VS1033 - MP3/AAC/WMA/MIDI AUDIO CODEC - VLSI Solution

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