3-Phase BLDC Motor Sensorless Control Using MC56F8013

Freescale Hybrid Controller Advantages and Features• Phase locked loop based frequency synthesizer for the hybrid controller core clock, with on-chiprelaxation oscillatorTable 1-1. Memory Configuration for the MC56F801x familyMC56F8011 MC56F8012 MC56F8013 MC56F8014Program Flash 12K x 16-bit 12K x 16-bit 16K x 16-bit 16K x 16-bitProgram RAM 2K x 16-bit 2K x 16-bit 4K x 16-bit 4K x 16-bitData RAM 2K x 16-bit 2K x 16-bit 4K x 16-bit 4K x 16-bitBLDC motor control benefits greatly from the flexible PWM module, fast ADC, and quadrature timermodule.The PWM offers flexibility in its configuration, enabling efficient control of the BLDC motor. The PWMblock has the following features:• Three complementary PWM signal pairs, six independent PWM signals, or a mixture thereof• Complementary channel operation features• Independent top and bottom deadtime insertion (MC56F8013 and later devices)• Separate top and bottom pulse width correction via current status inputs or software• Separate top and bottom polarity control• Edge-aligned or center-aligned PWM reference signals• 15-bit resolution• Half-cycle reload capability• Integral reload rates from one to sixteen period• Mask/swap capability• Individual, software-controlled PWM output• Programmable fault protection• Polarity control• 10/16mA current sink capability on PWM pins• Write-protectable registersThe PWM module is capable of providing six PWM signals with bipolar switching (the diagonal powerswitches are driven by the same signal). In addition, the PWM provides six-step BLDC commutationcontrol (where one motor phase is left unpowered so that the back-EMF can be detected). The PWM dutycycle can be set asynchronously to the commutation of the motor phases event using the channel swapfeature.The ADC module has the following features:• 12-bit resolution• Dual ADCs per module; three input channels per ADC• Maximum ADC clock frequency is 5.33 MHz with 187 ns period• Sampling rate up to 1.78 million samples per second• Single conversion time of 8.5 ADC clock cycles (8.5 x 187 ns = 1.59 ms)• Additional conversion time of six ADC clock cycles (6 x 187 ns = 1.125 ms)• Eight conversions in 26.5 ADC clock cycles (26.5 x 187 ns = 4.97 ms) using parallel mode• Can be synchronized to the PWM via the SYNC input signal provided the integration permits thePWM to trigger a timer channel connected to that input3-Phase BLDC Motor Sensorless Control using MC56F8013, Rev. 0Freescale Semiconductor 11