SD Specifications Part 1 UHS-II Simplified Addendum - SD Association

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UHS-II Simplified Addendum Version 1.01©Copyright 2010-2013 SD Card AssociationAppendix B (Normative) : Special TermsB.1 Terminology2L-HD modeHalf Duplex with 2 Lanes mode8b/10bOne of line coding that maps 8-bit symbols to 10-bit symbols to achieve DCbalanceand bounded disparity.BlockData unit to be transmitted by one DATA packetBlock LengthData length for one BlockBoot CodeCode including initial set of operations using bootstrapping processBoot Code Loading Transmitting Boot Code from Boot Device to Host immediately after PHYInitializationBoot DeviceDevice that stores Boot CodebroadcastOperating to all connecting nodes (Devices)BUSY periodPeriod that Host cannot access to backend (flash memory for SD-memory)CardSD memory cardCMCommon ModeCM-TRANCommon transaction layer in UHS-IICommand Time Slot Time period that FULL_RESET, TRANS_ABORT, and arbitrary read CCMDare allowed to be issued on the way of data transmissionConfigurationAn arrangement of functional unit or parameters according to capabilities ofHost and DevicesDATA BurstA unit that consists of one or more DATA packets and related LSS and canbe sent in one flow control unitDATA Burst Streaming Bypassing DATA Bursts to the next Node without passing through LINK.De-embedding Removing the effect of unwanted component from the measurement resultDeviceThe electrical equipment which transmit/receive data to/from Host andcommunication is controlled by Host. Device includes Card and EmbeddedDeviceDevice Initialization Process to make Device enable its all functionsdownstreamTransmission from Host to DeviceEmbedded Device Non-removable SD Device without form factorEnumerationAssigning Node ID for each connecting DeviceFD modeFull Duplex modeFlow ControlProcess of managing the data transmission to prevent data overflow orunderflow.Flow Control Unit A unit of period for data transmission accompanied by FCREQ-FCRDYhandshake. Also refer to DATA Burst.Fractional DATA Burst A DATA Burst which consists of Framed DATA packet less than N_FCUFramingPrefixing SOP and postfixing EOP for packets, and prefixing SDB andpostfixing EDB for DATA Burst.Full Duplex mode Communication mode that the direction of two Lanes is opposite each other.Half Duplex with 2Lanes modeCommunication mode that the direction of two Lanes is same. It is optionalin UHS-II.Host The electrical equipment which transmit/receive data to/from Device (e. g.SD Card) and control the communication. Only Host can issue commands.HubDevice that allows many Devices to be connected to a single port on a HostI/F power cycle Act of turning whole UHS-II interface off and then on again by I/F power92
UHS-II Simplified Addendum Version 1.01©Copyright 2010-2013 SD Card AssociationI/F power supplyInter skewIntra skewJitterLaneLegacy SDLineLINKLoopbackNodeNode IDPacket bypassingParallel terminationPHYReturn lossRxSD-TRANSerializer/DeserializerskewTRANtransactionTxUHS-II CardUHS-II nativeupstreamWakeupX5R,X7RsupplyPower supplement for UHS-II interface (e.g. VDD2 for SD-memory)The skew between differential Lanes transmitting in same direction.The skew between Positive Line signal and Negative Line signal of onedifferential pair.Jitter is undesirable time variation of a periodic signal, which is caused by ISIand some fluctuations such as voltage supply and temperature etc.Each set which consists of Tx Port, transmission Line and Rx Port. Forexample, D0 consists of D0.Tx in Host, D0 Line and D0.Rx in Device.SD card not supporting UHS-II interfaceComponent for connecting a Tx (Transmitter) Port and an Rx (Receiver) Portand realizing differential transmissionThe interface layer above PHY Layer. LINK is in charge of controlling dataflow and making management for LINK and PHY.Method or procedure of routing electronic signals from their originatingfacility quickly back to the same source entity without intentional processingor modificationHost or DeviceNumber to identify NodesSending packets to the next Node without any operations in TRANTermination connecting positive and negative Lines of a differential LanePhysical Interface LayerReflection ratio of signal power in a transmission LineReceiver Circuit, which is responsible for outputting differential signalOne of application specific layers in UHS-II. It bridges CM-TRAN and LegacySD applications or drivers.A pair of functional blocks to compensate for limited input/output. Theseblocks convert data between serial data and parallel interfaces in eachdirection.Time difference of transmission delay between two transmission LinesThe interface layer above LINK. It is divided into CM-TRAN and anapplication specific TRAN.A unit of communication that takes place by one commandTransmitter circuit, which is responsible for outputting differential signalSD card supporting UHS-II InterfaceUHS-II without (or not considering) application specific layersTransmission from Device to HostPHY initialization stateSymbol for dielectric material of capacitorsB.2 AbbreviationsBSYNCCMDCDCPCFCFG_REGSynchronization for Boot Code LoadingControl CommandCandidate DCPCompletion Flag of Device InitializationConfiguration Register93
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SD Specifications Part 1 UHS-II Simplified Addendum - SD Association

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