SD Specifications Part 1 UHS-II Simplified Addendum - SD Association
SD Specifications Part 1 UHS-II Simplified Addendum - SD Association
SD Specifications Part 1 UHS-II Simplified Addendum - SD Association
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<strong>UHS</strong>-<strong>II</strong> <strong>Simplified</strong> <strong>Addendum</strong> Version 1.01©Copyright 2010-2013 <strong>SD</strong> Card <strong>Association</strong>4.7.3 Test ModesParameters for entering each Test mode are described as follows. The sequences for entering each testmode are shown in Figure 4-21 and Figure 4-22.TMD1 Modes: 00h: Normal Mode At OnceSetting in Sub Modes 03-01(Normal Mode) is effective immediately.After entering a test mode, it is possible to go back to Dormant state. 01h: Normal Mode Through Dormant stateSetting in Sub Modes 03-01(Normal Mode) is effective when exiting Dormant state.After entering a test mode, it is possible to go back to Dormant state. 02h: Disconnect Mode At OnceSetting in Sub Modes 03-01 (Disconnect Mode) is effective immediately.After entering a test mode, the Device cannot go Dormant state. 03h: Disconnect Mode Through Dormant stateSetting in Sub Modes 03-01 (Disconnect Mode) is effective when exiting Dormant state.After entering a test mode, the Device cannot go Dormant state.TMD2 Modes:PLL Multiplier (Bit 02-00) 000b: x15 001b:x30 010b-111b: ReservedChange of this field is effective when exiting Dormant or Re-Sync state. Clock frequency maybe changed only during Dormant or Re-Sync state.Loop Back Direction (Bit 07) 0b: Forward Loop Back (means from D0.Rx to D1.Tx) 1b: Backward Loop Back (means from D1.Rx to D0.Tx)When this bit is changed, both D0 and D1 are set to input mode immediately.28