SD Specifications Part 1 UHS-II Simplified Addendum - SD Association

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UHS-II Simplified Addendum Version 1.01©Copyright 2010-2013 SD Card Association4.3.3 Eye-mask TemplateThe eye-mask templates are the graphical representation of the limit for the voltage and jitter for thedifferential signals. The eye-mask templates of UHS-II are shown in Figure 4-6. The horizontal margin ofeye-mask template is calculated as 1 UI - T J .For the transmitters of Host and Device, when transmitting differential signal, these signals includingover/under-shoot shall remain in the white area of each Eye-mask template (Tx) in Figure 4-6 at anytime except in EIDL state.For the receivers of Host and Device, when receiving the differential signals that have the eye-openingshown in eye-templates (Rx) in Figure 4-6, receivers shall receive these signals correctly.The eye mask templates specified in Figure 4-6 refers to measurements at standard measurementconditions and BER of 1E-12. The standard measurement conditions are described in UHS-II PHY TestGuideline document.Note: The Host and Device are tested separately at "ideal" compliance environment, while in realsystem Host and Device are connected together, so there will be some mutual effects because ofthis connection. The margin between (2) to (3) Eye-masks and (4) Eye-mask to (5) Eye-mask aretaken because of that. The following elements are covered by this margin:A. Power delivery noise,B. Internal Device Xtalk due to other internal activityHost Compliance test environmentDevice Compliance test environment(1) Eye-mask for Host Transmitter at TP1(2) Eye-mask for Host Transmitter at TP2(3) Eye-mask for Device Receiver at TP2Differential Swing [mV]2801400-1400.75UITxDifferential Swing [mV]2801250-1250.65UITxDifferential Swing [mV]950-950.6UIRx-2800.375UI-2800 0.125 0.3125 0.5 0.6875 0.875Unit Interval [UI]Eye-mask at TP1 is design guide0 0.175 0.5 0.825Unit Interval [UI]0 0.2 0.5 0.8Unit Interval [UI]Card Test Fixture PCBHostRCLKHost Test Fixture PCBLSIRCLKLSITxD0RxD0TxRxD1PCBUHS-II SD CardSocketHost PCBSocketD1TP1TP2TP2(6) Eye-mask for Host Receiver at TP1 (5) Eye-mask for Host Receiver at TP2(4) Eye-mask for Device Transmitter at TP2Differential Swing [mV]950-950.5UIRx0 0.25 0.5 0.75Unit Interval [UI]Eye-mask at TP1 is design guideDifferential Swing [mV]0.6UI1100Rx-1100.3UI0 0.2 0.35 0.5 0.65 0.8Unit Interval [UI]Differential Swing [mV]2800.65UI1400Tx-1400.325UI-2800 0.175 0.3375 0.5 0.6625 0.825Unit Interval [UI]Figure 4-6: Eye-mask TemplatesNotes of Figure 4-6 is a blank in the Simplified Addendum.18
UHS-II Simplified Addendum Version 1.01©Copyright 2010-2013 SD Card Association4.3.4 JitterThe relation between eye-opening and total jitter is defined by Eye Opening = 1UI- T J . The more jitter,the less eye-opening. Thus, for ensuring the interconnection between Host and Device, jitterspecification shall be adhered for each differential Lane: RCLK, D0 and D1.Total Jitter T J consists of two jitter components: deterministic peak to peak jitter D J and random rootmean square jitter R J-rms .Total Jitter T J is calculated by the following equation:T D Q RJJJ _ rmsWhere, Q factor is related to Bit error rate (BER). In UHS-II, BER performance of PHY shall be achievedby 10 -12, when Q is 14.1.The D J contains two elements D J (ISI) which is the deterministic jitter caused by ISI and S J which is asinusoidal jitter component.Test pattern, jitter element budgeting and jitter injection method is specified in UHS-II PHY TestGuideline document.Section 4.3.4.1 to Section 4.3.4.2 is a blank in the Simplified Addendum.Host Compliance test environmentHostHost Test Fixture PCBDevice Compliance test environment(1)Jitter Tolerance for Device Receiver at TP2RCLKT J ptp = S J_ptp + D J (ISI) _ptp + Q*R J_rmsLSID0TP1D1Host PCBTP2SocketJitter Components (ptp) [UI]234KS-20dB/decadeDJ(ISI) and Q*RJ_rmsSJ2.34M RLCKS FrequencyFrequency [Hz](2)Jitter Tolerance for Host Receiver at TP2T J ptp = S J_ptp + D J (ISI) _ptp + Q*R J_rmsJitter Components (ptp) [UI]234KS-20dB/decadeDJ(ISI) and Q*RJ_rmsSJ2.34M RLCKS FrequencyFrequency [Hz]Frequency [Hz] TJ ptp [UI] SJ ptp [UI]234KSf2.34MSfRLCK FrequencyRCLKD01.30.40.4D0 to RCLK Relative jitterCard Test Fixture PCBLSI1.00.10.1Frequency [Hz] TJ ptp [UI] SJ ptp [UI]234KSf2.34MSfRLCK Frequency1.30.40.41.00.10.1D1TP2SocketPCBUHS-II SD CardFigure 4-7: Jitter Tolerance SpecificationNotes of Figure 4-7 is a blank in the Simplified Addendum.19
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SD Specifications Part 1 UHS-II Simplified Addendum - SD Association

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