SD Specifications Part 1 UHS-II Simplified Addendum - SD Association

UHS-II Simplified Addendum Version 1.01©Copyright 2010-2013 SD Card Association4.7.2 Definition of TMD1 and TMD2The structure of TMD1 and TMD2 are defined as follows and in Figure 4-20. Device maintains setting ofTMD1 and TMD2 during PHY test mode until Host changes setting of TMD1 and TMD2, even if goingthrough Dormant or Re-Sync mode.4.7.2.1 TMD1TMD1 is used for configuring Main mode and Sub mode.Upper 4-bit is used to assign Main Mode: 0h : assigned for Loop Back Test Modes Fh : assigned for vendor specific test modes (Vendor may define TMD1 and TMD2to control vendor specific test modes)Lower 4-bit is used to assign Sub Mode: "Timing"(Sub Mode 00): determines the timing when Sub-Mode 03-01 is effective. "Disconnect"(Sub Mode 01): determines whether Disconnected modeor Normal (Non-Disconnect mode).4.7.2.2 TMD2TMD2 is specified by each Main Mode."Loop Back Direction"(07): determines whether Forward Loop back or Backward Loop back.When this bit is changed, the change of Loop Back Direction is done immediately.Everytime Loopback direction is changed, both D0 and D1 are set to input at firstin order to re-connect Test tool.After re-connecting Test tool to Device/Host:- After Device detects SYN from D1, D0 is enabled as output,and then the change of Loopback direction is done.- After Host detects SYN from D0, D1 is enabled as output,and then the change of Loopback direction is done.- After Device detects SYN from D0, D1 is enabled as output,and then the change of Loopback direction is done.- After Host detects SYN from D1, D0 is enabled as output,and then the change of Loopback direction is done. "SSCE"(06): controls Host SSC On/Off if Host supports SSC function. This bit is not effective toDevice."PLL Multiplier factor"(02-00): determines PLL Multiplier (x15 or x30). The actualchange of PLL Multiplier is done after exiting Dormant or Re-Sync state.26