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SD Specifications Part 1 UHS-II Simplified Addendum - SD Association

SD Specifications Part 1 UHS-II Simplified Addendum - SD Association

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<strong>UHS</strong>-<strong>II</strong> <strong>Simplified</strong> <strong>Addendum</strong> Version 1.01©Copyright 2010-2013 <strong>SD</strong> Card <strong>Association</strong>If Host intends to use <strong>UHS</strong>-<strong>II</strong> interface, it supplies VDD2, RCLK and VDD1 after power up, and setsSTB.L on D0.Tx. Device connects termination resistors of RCLK Lanes after power up. Device startsPHY Initialization when receiving STB.L and responds STB.L if it succeeds.The method for Host to distinguish whether Device fails to start PHY initialization is through detectingtimeout from Host's setting STB.L on D0.Tx to receiving it on D1.Rx, which can be estimated fromTeidl_stb and <strong>UHS</strong>-<strong>II</strong> bus topology.If Host detects timeout, Host sets RCLK Lane to DIF-Z to stop supplying RCLK, and then Host supplies<strong>SD</strong>CLK and issues CMD8 and ACMD41 for Legacy <strong>SD</strong> protocol to initialize <strong>SD</strong> interface. Then, Hostproceeds card identification and the card status transits to "data transfer mode" in Legacy <strong>SD</strong> (same asdata transfer mode defined in <strong>SD</strong> <strong>Specifications</strong> <strong>Part</strong> 1 Physical Layer <strong>Simplified</strong> Specification Version4.10) as a result. When Legacy <strong>SD</strong> interface is selected, <strong>UHS</strong>-<strong>II</strong> interface that is activated by power upis disabled before ACMD41 is completed. Moreover, termination resistors of RCLK Lanes in Device aredisconnected when disabling <strong>UHS</strong>-<strong>II</strong> interface. As the sequence to "data transfer mode" in Legacy <strong>SD</strong> inFigure 7-11 is simplified, refer to <strong>SD</strong> <strong>Specifications</strong> <strong>Part</strong> 1 Physical Layer <strong>Simplified</strong> SpecificationVersion 4.10 for detailed specifications of Legacy <strong>SD</strong> initialization. Note that if CMD0 is issued inLegacy <strong>SD</strong> card state transits to 'idle'. (Note that it is impossible to execute (<strong>UHS</strong>-<strong>II</strong>) PHY Initialization.)On the other hand, if Device succeeds PHY Initialization, <strong>UHS</strong>-<strong>II</strong> interface is available and then, DeviceInitialization, Enumeration and Configuration take place in this order. If Host detects "Application Type"is "<strong>SD</strong> memory" or "<strong>SD</strong>IO" during Configuration, it can issue the encapsulated <strong>SD</strong> CMD. Host shallexecute card identification described in Section 7.2.4.1 by encapsulated <strong>SD</strong> CMDs in case of detecting"<strong>SD</strong> memory". If encapsulated CMD0 is issued, card state transits to 'idle' in <strong>SD</strong>-TRAN. On the otherhand, if FULL_RESET CCMD is issued, Device waits STB.L for PHY Initialization.If Host intends to use only Legacy <strong>SD</strong> interface or detects that Legacy <strong>SD</strong> Card is inserted, it is allowedto supply only VDD1 and <strong>SD</strong>CLK, and issue CMD8 in order to accelerate initialization of Legacy <strong>SD</strong>interface. Note that once <strong>UHS</strong>-<strong>II</strong> I/F is disabled, Host requires power cycle to enable <strong>UHS</strong>-<strong>II</strong> again.Refer to Section 3.10.4 in <strong>SD</strong> Specification <strong>Part</strong> 1 Version 4.00 for more details about VDD2 supply.Note that Device's power consumption during Device Initialization is not regulated by Power Limitspecified by CMD6, but parameters specified by DEVICE_INIT CCMD.7.2.3.3 Interface Selection after FULL_RESET or GO_DORMANT_STATEFigure 7-12 shows a concept diagram of initialization flow after executing FULL_RESET orGO_DORMANT_STATE CCMD.84

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