Xilinx UG230 Spartan-3E FPGA Starter Kit Board User Guide

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Chapter 12: SPI Serial Flash Additional Design Details SF_A SF_A SF_A (T16) (U15) (V15) After programming the SPI Flash, remove jumper JP8, as shown in Figure 12-16a. If properly programmed, the FPGA then configures itself from the SPI Flash PROM and the DONE LED lights. The DONE LED is shown in Figure 12-3. Figure 12-17 provides additional details of the SPI Flash interface used on the Spartan-3E Starter Kit board. In most applications, this interface is as simple as that shown in Figure 12-1. The Spartan-3E Starter Kit board, however, supports of variety of configuration options and demonstrates additional Spartan-3E FPGA capabilities. Spartan-3E FPGA MOSI/CSI_B (T4) VS2/A17 DIN/D0 (N10) VS1/A18 VS0/A19 CCLK CSO_B (U16) (U3) User-I/O (R12) Figure 12-17: Additional SPI Flash Interface Design Details Shared SPI Bus with Peripherals SPI_MOSI SPI_MISO SPI_SCK SPI_SS_B SPI_ALT_CS_JP11 Jumper J11 Programming Header J12 CSO_B SEL ROM_CS CSO_B SEL SDI SDO SCK GND 3.3V STMicro M25P16 SPI Serial Flash D After configuration, the SPI Flash configuration pins are available to the application. On the Spartan-3E Starter Kit board, the SPI bus is shared by other SPI-capable peripheral devices, as shown in Figure 12-17. To access the SPI Flash memory after configuration, the FPGA application must disable the other devices on the shared PCI bus. Table 12-3 shows the signal names and disable values for the other devices. 100 www.xilinx.com Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.2) January 20, 2011 Q C S DAC AMP ADC Platform Flash Strata- Flash W HLD Other devices share SPI bus 3.3V UG230_c15_17_030306 R
R Other SPI Flash Control Signals Additional Design Details The M25P16 SPI Flash has two additional control inputs. The active-Low write protect input (W) and the active-Low bus hold input (HLD) are unused and pulled High via an external pull-up resistor. Variant Select Pins, VS[2:0] Jumper Block J11 Table 12-3: Disable Other Devices on SPI Bus When in SPI configuration mode, the FPGA samples the value on three pins, labeled VS[2:0], to determine which SPI read command to issue to the SPI Flash. For the M25P16 Flash, VS[2:0]= issues the correct command sequence. The VS[2:0] pins are pulled High externally via pull-up resistors to 3.3V. The VS[2:0] pins are also parallel NOR Flash address lines A[19:17] in the FPGA’s BPI configuration mode and these signals also connect to the StrataFlash parallel Flash PROM. After SPI configuration, the VS[2:0] pins become user-programmable I/O pins, allowing full access to the StrataFlash PROM, despite that the FPGA configured from SPI Flash. In SPI configuration mode, the FPGA selects the attached SPI Flash by asserting the CSO_B pin Low. On the Spartan-3E Starter Kit board, the CSO_B pin drives into the jumper J11 block. This jumper block provides the option to move the on-board SPI Flash to a different select line (SPI_ALT_CS_JP11). This way, a different SPI Flash device can be tested by changing the JP11 jumper settings and connecting the alternate SPI Flash on Header JP12. By default, both jumpers are inserted on jumper block header J11. Programming Header J12 As shown in Figure 12-15, page 99, Header J12 accepts a JTAG parallel programming cable to program the on-board SPI Flash. Multi-Package Layout Signal Disabled Device Disable Value DAC_CS Digital-to-Analog Converter (DAC) 1 AMP_CS Programmable Pre-Amplifier 1 AD_CONV Analog-to-Digital Converter (ADC) 0 SF_CE0 StrataFlash Parallel Flash PROM 1 FPGA_INIT_B Platform Flash PROM 0 STMicroelectronics was rather clever when they defined the package layout for the M25Pxx SPI serial Flash family. The Spartan-3E Starter Kit board supports all three of the package types used for the 16 Mbit device, as shown in Figure 12-18. By default, the board ships with the 8-lead, 8x6 mm MLP package. The multi-package layout also supports the 8pin SOIC package and the 16-pin SOIC package. Pin 1 for the 8-pin SOIC and MLP packages is located in the top-left corner. However, pin 1 for the 16-pin SOIC package is located in the top-right corner, because the package is rotated 90°. The 16-pin SOIC package also have four pins on each side that do not connect on the board. These pins must Spartan-3E FPGA Starter Kit Board User Guide www.xilinx.com 101 UG230 (v1.2) January 20, 2011
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Spartan-3E FPGA Starter Kit Board U
Page 3 and 4:
Table of Contents Preface: About Th
Page 5 and 6:
R Writing Data to the Display . . .
Page 7 and 8:
R UCF Location Constraints . . . .
Page 9 and 10:
R About This Guide Acknowledgements
Page 11 and 12:
R Introduction and Overview Chapter
Page 13 and 14:
R Design Trade-Offs Design Trade-Of
Page 15 and 16:
R Switches, Buttons, and Knob Slide
Page 17 and 18:
R Rotary Push-Button Switch In some
Page 19 and 20:
A Rotating RIGHT B Detent R Discret
Page 21 and 22:
R Clock Sources Overview Chapter 3
Page 23 and 24:
R Clock Period Constraints Related
Page 25 and 26:
R FPGA Configuration Options Chapte
Page 27 and 28:
R Configuration Mode Jumpers The co
Page 29 and 30:
R Programming the FPGA, CPLD, or Pl
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Page 33 and 34:
Page 35 and 36:
Page 37 and 38:
Page 39 and 40:
Page 41 and 42:
R Related Resources Figure 4-26: PR
Page 43 and 44:
R Character LCD Screen Overview Cha
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R UCF Location Constraints LCD Cont
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R LCD Controller The character ROM
Page 49 and 50: R Disabled If the LCD_E enable sign
Page 51 and 52: R Table 5-4: Shift Patterns Accordi
Page 53 and 54: R Operation The data values on SF_D
Page 55 and 56: R VGA Display Port 1 2 3 4 5 6 11 7
Page 57 and 58: time HS R Current through the horiz
Page 59 and 60: R UCF Location Constraints Related
Page 61 and 62: R RS-232 Serial Ports Overview Chap
Page 63 and 64: R PS/2 Mouse/Keyboard Port Chapter
Page 65 and 66: ESC 76 ` ~ 0E TA B 0D Caps Lock 58
Page 67 and 68: R Voltage Supply UCF Location Const
Page 69 and 70: R Digital to Analog Converter (DAC)
Page 71 and 72: R Table 9-2: Disabled Devices on th
Page 73 and 74: R UCF Location Constraints Related
Page 75 and 76: R Analog Capture Circuit Chapter 10
Page 77 and 78: R Programmable Pre-Amplifier Finall
Page 79 and 80: R Analog to Digital Converter (ADC)
Page 81 and 82: R Disable Other Devices on the SPI
Page 83 and 84: R Chapter 11 Intel StrataFlash Para
Page 85 and 86: R Table 11-1: FPGA-to-StrataFlash C
Page 87 and 88: R Shared Connections Character LCD
Page 89 and 90: R Control Setting the FPGA Mode Sel
Page 91 and 92: R SPI Serial Flash UCF Location Con
Page 93 and 94: R Creating an SPI Serial Flash PROM
Page 95 and 96: R Configuring from SPI Flash Figure
Page 97 and 98: R Configuring from SPI Flash To gen
Page 99: R Insert Jumper on JP8 and Hold PRO
Page 103 and 104: R Related Resources Related Resourc
Page 105 and 106: R DDR SDRAM 5.0V LTC3412 Chapter 13
Page 107 and 108: R Table 13-1: FPGA-to-DDR SDRAM Con
Page 109 and 110: R Control Related Resources Figure
Page 111 and 112: R Chapter 14 10/100 Ethernet Physic
Page 113 and 114: R MicroBlaze Ethernet IP Cores Tabl
Page 115 and 116: R Expansion Connectors Chapter 15 T
Page 117 and 118: R Table 15-1: Hirose 100-pin FX2 Co
Page 119 and 120: R Table 15-2: Differential I/O Pair
Page 121 and 122: R Using Differential Outputs Hirose
Page 123 and 124: R Six-Pin Accessory Headers Header
Page 125 and 126: R Connectorless Debugging Port Land
Page 127 and 128: R XC2C64A CoolRunner-II CPLD Chapte
Page 129 and 130: R UCF Location Constraints UCF Loca
Page 131 and 132: R DS2432 1-Wire SHA-1 EEPROM UCF Lo
Page 133 and 134: Schematics R This appendix provides
Page 135 and 136: R FX2 Expansion Header, 6-pin Heade
Page 137 and 138: R Figure A-2: Schematic Sheet 2 RS-
Page 139 and 140: R Figure A-3: Schematic Sheet 4 Eth
Page 141 and 142: R Figure A-4: Schematic Sheet 5 Vol
Page 143 and 144: R FPGA Configurations Settings, Pla
Page 145 and 146: R Figure A-6: Schematic Sheet 7 FPG
Page 147 and 148: R Figure A-7: Schematic Sheet 8 FPG
Page 149 and 150: R Figure A-8: Schematic Sheet 9 Pow
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R Figure A-9: Schematic Sheet 10 XC
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R Figure A-10: Schematic Sheet 11 L
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R Intel StrataFlash Parallel NOR Fl
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R Buttons, Switches, Rotary Encoder
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R DDR SDRAM Series Termination and
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R Appendix B Example User Constrain
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R NET "FX2_IO" LOC = "A16" | IOSTAN
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R NET "SD_LDM" LOC = "J2" | IOSTAND
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Xilinx UG230 Spartan-3E FPGA Starter Kit Board User Guide

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