Xilinx UG230 Spartan-3E FPGA Starter Kit Board User Guide

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Chapter 6: VGA Display Port Table 6-1: 3-Bit Display Color Codes VGA_RED VGA_GREEN VGA_BLUE Resulting Color 0 0 0 Black 0 0 1 Blue 0 1 0 Green 0 1 1 Cyan 1 0 0 Red 1 0 1 Magenta 1 1 0 Yellow 1 1 1 White VGA signal timing is specified, published, copyrighted, and sold by the Video Electronics Standards Association (VESA). The following VGA system and timing information is provided as an example of how the FPGA might drive VGA monitor in 640 by 480 mode. For more precise information or for information on higher VGA frequencies, refer to documents available on the VESA website or other electronics websites (see “Related Resources,” page 59). Signal Timing for a 60 Hz, 640x480 VGA Display CRT-based VGA displays use amplitude-modulated, moving electron beams (or cathode rays) to display information on a phosphor-coated screen. LCDs use an array of switches that can impose a voltage across a small amount of liquid crystal, thereby changing light permittivity through the crystal on a pixel-by-pixel basis. Although the following description is limited to CRT displays, LCDs have evolved to use the same signal timings as CRT displays. Consequently, the following discussion pertains to both CRTs and LCDs. Within a CRT display, current waveforms pass through the coils to produce magnetic fields that deflect electron beams to transverse the display surface in a raster pattern, horizontally from left to right and vertically from top to bottom. As shown in Figure 6-2, information is only displayed when the beam is moving in the forward direction—left to right and top to bottom—and not during the time the beam returns back to the left or top edge of the display. Much of the potential display time is therefore lost in blanking periods when the beam is reset and stabilized to begin a new horizontal or vertical display pass. 56 www.xilinx.com Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.2) January 20, 2011 R
time HS R Current through the horizontal deflection coil "front porch" pixel 0,0 VGA Display Stable current ramp: Information is displayed during this time Total horizontal time Horizontal display time Horizontal sync signal sets the retrace frequency Figure 6-2: CRT Display Timing Example Signal Timing for a 60 Hz, 640x480 VGA Display pixel 0,639 640 pixels are displayed each time the beam traverses the screen pixel 479,0 pixel 479,639 retrace time Retrace: No information is displayed during this time "front porch" "back porch" UG230_c6_02_021706 The display resolution defines the size of the beams, the frequency at which the beam traces across the display, and the frequency at which the electron beam is modulated. Modern VGA displays support multiple display resolutions, and the VGA controller dictates the resolution by producing timing signals to control the raster patterns. The controller produces TTL-level synchronizing pulses that set the frequency at which current flows through the deflection coils, and it ensures that pixel or video data is applied to the electron guns at the correct time. Video data typically comes from a video refresh memory with one or more bytes assigned to each pixel location. The Spartan-3E FPGA Starter Kit board uses three bits per pixel, producing one of the eight possible colors shown in Table 6-1. The controller indexes into the video data buffer as the beams move across the display. The controller then retrieves and applies video data to the display at precisely the time the electron beam is moving across a given pixel. Spartan-3E FPGA Starter Kit Board User Guide www.xilinx.com 57 UG230 (v1.2) January 20, 2011
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Spartan-3E FPGA Starter Kit Board U
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Table of Contents Preface: About Th
Page 5 and 6: R Writing Data to the Display . . .
Page 7 and 8: R UCF Location Constraints . . . .
Page 9 and 10: R About This Guide Acknowledgements
Page 11 and 12: R Introduction and Overview Chapter
Page 13 and 14: R Design Trade-Offs Design Trade-Of
Page 15 and 16: R Switches, Buttons, and Knob Slide
Page 17 and 18: R Rotary Push-Button Switch In some
Page 19 and 20: A Rotating RIGHT B Detent R Discret
Page 21 and 22: R Clock Sources Overview Chapter 3
Page 23 and 24: R Clock Period Constraints Related
Page 25 and 26: R FPGA Configuration Options Chapte
Page 27 and 28: R Configuration Mode Jumpers The co
Page 29 and 30: R Programming the FPGA, CPLD, or Pl
Page 41 and 42: R Related Resources Figure 4-26: PR
Page 43 and 44: R Character LCD Screen Overview Cha
Page 45 and 46: R UCF Location Constraints LCD Cont
Page 47 and 48: R LCD Controller The character ROM
Page 49 and 50: R Disabled If the LCD_E enable sign
Page 51 and 52: R Table 5-4: Shift Patterns Accordi
Page 53 and 54: R Operation The data values on SF_D
Page 55: R VGA Display Port 1 2 3 4 5 6 11 7
Page 59 and 60: R UCF Location Constraints Related
Page 61 and 62: R RS-232 Serial Ports Overview Chap
Page 63 and 64: R PS/2 Mouse/Keyboard Port Chapter
Page 65 and 66: ESC 76 ` ~ 0E TA B 0D Caps Lock 58
Page 67 and 68: R Voltage Supply UCF Location Const
Page 69 and 70: R Digital to Analog Converter (DAC)
Page 71 and 72: R Table 9-2: Disabled Devices on th
Page 73 and 74: R UCF Location Constraints Related
Page 75 and 76: R Analog Capture Circuit Chapter 10
Page 77 and 78: R Programmable Pre-Amplifier Finall
Page 79 and 80: R Analog to Digital Converter (ADC)
Page 81 and 82: R Disable Other Devices on the SPI
Page 83 and 84: R Chapter 11 Intel StrataFlash Para
Page 85 and 86: R Table 11-1: FPGA-to-StrataFlash C
Page 87 and 88: R Shared Connections Character LCD
Page 89 and 90: R Control Setting the FPGA Mode Sel
Page 91 and 92: R SPI Serial Flash UCF Location Con
Page 93 and 94: R Creating an SPI Serial Flash PROM
Page 95 and 96: R Configuring from SPI Flash Figure
Page 97 and 98: R Configuring from SPI Flash To gen
Page 99 and 100: R Insert Jumper on JP8 and Hold PRO
Page 101 and 102: R Other SPI Flash Control Signals A
Page 103 and 104: R Related Resources Related Resourc
Page 105 and 106: R DDR SDRAM 5.0V LTC3412 Chapter 13
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R Table 13-1: FPGA-to-DDR SDRAM Con
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R Control Related Resources Figure
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R Chapter 14 10/100 Ethernet Physic
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R MicroBlaze Ethernet IP Cores Tabl
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R Expansion Connectors Chapter 15 T
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R Table 15-1: Hirose 100-pin FX2 Co
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R Table 15-2: Differential I/O Pair
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R Using Differential Outputs Hirose
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R Six-Pin Accessory Headers Header
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R Connectorless Debugging Port Land
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R XC2C64A CoolRunner-II CPLD Chapte
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R UCF Location Constraints UCF Loca
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R DS2432 1-Wire SHA-1 EEPROM UCF Lo
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Schematics R This appendix provides
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R FX2 Expansion Header, 6-pin Heade
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R Figure A-2: Schematic Sheet 2 RS-
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R Figure A-3: Schematic Sheet 4 Eth
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R Figure A-4: Schematic Sheet 5 Vol
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R FPGA Configurations Settings, Pla
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R Figure A-6: Schematic Sheet 7 FPG
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R Figure A-7: Schematic Sheet 8 FPG
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R Figure A-8: Schematic Sheet 9 Pow
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R Figure A-9: Schematic Sheet 10 XC
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R Figure A-10: Schematic Sheet 11 L
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R Intel StrataFlash Parallel NOR Fl
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R Buttons, Switches, Rotary Encoder
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R DDR SDRAM Series Termination and
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R Appendix B Example User Constrain
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R NET "FX2_IO" LOC = "A16" | IOSTAN
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R NET "SD_LDM" LOC = "J2" | IOSTAND
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Xilinx UG230 Spartan-3E FPGA Starter Kit Board User Guide

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