Xilinx UG230 Spartan-3E FPGA Starter Kit Board User Guide

Chapter 13: DDR SDRAM
UCF Location Constraints
Address
Data
Figure 13-2 provides the User Constraint File (UCF) constraints for the DDR SDRAM
address pins, including the I/O pin assignment and the I/O standard used.
NET "SD_A" LOC = "P2" | IOSTANDARD = SSTL2_I ;
NET "SD_A" LOC = "N5" | IOSTANDARD = SSTL2_I ;
NET "SD_A" LOC = "T2" | IOSTANDARD = SSTL2_I ;
NET "SD_A" LOC = "N4" | IOSTANDARD = SSTL2_I ;
NET "SD_A" LOC = "H2" | IOSTANDARD = SSTL2_I ;
NET "SD_A" LOC = "H1" | IOSTANDARD = SSTL2_I ;
NET "SD_A" LOC = "H3" | IOSTANDARD = SSTL2_I ;
NET "SD_A" LOC = "H4" | IOSTANDARD = SSTL2_I ;
NET "SD_A" LOC = "F4" | IOSTANDARD = SSTL2_I ;
NET "SD_A" LOC = "P1" | IOSTANDARD = SSTL2_I ;
NET "SD_A" LOC = "R2" | IOSTANDARD = SSTL2_I ;
NET "SD_A" LOC = "R3" | IOSTANDARD = SSTL2_I ;
NET "SD_A" LOC = "T1" | IOSTANDARD = SSTL2_I ;
Figure 13-2: UCF Location Constraints for DDR SDRAM Address Inputs
Figure 13-3 provides the User Constraint File (UCF) constraints for the DDR SDRAM data
pins, including the I/O pin assignment and I/O standard used.
NET "SD_DQ" LOC = "H5" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ" LOC = "H6" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ" LOC = "G5" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ" LOC = "G6" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ" LOC = "F2" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ" LOC = "F1" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ" LOC = "E1" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ" LOC = "E2" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ" LOC = "M6" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ" LOC = "M5" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ" LOC = "M4" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ" LOC = "M3" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ" LOC = "L4" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ" LOC = "L3" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ" LOC = "L1" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ" LOC = "L2" | IOSTANDARD = SSTL2_I ;
Figure 13-3: UCF Location Constraints for DDR SDRAM Data I/Os
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UG230 (v1.2) January 20, 2011
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