Xilinx UG230 Spartan-3E FPGA Starter Kit Board User Guide

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Chapter 5: Character LCD Screen This bit either auto-increments or auto-decrements the DD RAM and CG RAM address counter by one location after each Write Data to CG RAM or DD RAM or Read Data from CG RAM or DD RAM command. The cursor or blink position moves accordingly. Bit DB0: (S) Shift 0 Shifting disabled 1 During a DD RAM write operation, shift the entire display value in the direction controlled by Bit DB1 (I/D). Appears as though the cursor position remains constant and the display moves. Display On/Off Display is turned on or off, controlling all characters, cursor and cursor position character (underscore) blink. Execution Time: 40 μs Bit DB2: (D) Display On/Off 0 No characters displayed. However, data stored in DD RAM is retained 1 Display characters stored in DD RAM Bit DB1: (C) Cursor On/Off The cursor uses the five dots on the bottom line of the character. The cursor appears as a line under the displayed character. 0 No cursor 1 Display cursor Bit DB0: (B) Cursor Blink On/Off 0 No cursor blinking 1 Cursor blinks on and off approximately every half second Cursor and Display Shift Moves the cursor and shifts the display without changing DD RAM contents. Shift cursor position or display to the right or left without writing or reading display data. This function positions the cursor in order to modify an individual character, or to scroll the display window left or right to reveal additional data stored in the DD RAM, beyond the 16th character on a line. The cursor automatically moves to the second line when it shifts beyond the 40th character location of the first line. The first and second line displays shift at the same time. When the displayed data is shifted repeatedly, both lines move horizontally. The second display line does not shift into the first display line. Execution Time: 40 μs 50 www.xilinx.com Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.2) January 20, 2011 R
R Table 5-4: Shift Patterns According to S/C and R/L Bits Function Set Sets interface data length, number of display lines, and character font. The Starter Kit board supports a single function set with value 0x28. Execution Time: 40 μs Set CG RAM Address LCD Controller DB3 DB2 (S/C) (R/L) Operation 0 0 Shift the cursor position to the left. The address counter is decremented by one. 0 1 Shift the cursor position to the right. The address counter is incremented by one. 1 0 1 1 Set the initial CG RAM address. After this command, all subsequent read or write operations to the display are to or from CG RAM. Execution Time: 40 μs Set DD RAM Address Shift the entire display to the left. The cursor follows the display shift. The address counter is unchanged. Shift the entire display to the right. The cursor follows the display shift. The address counter is unchanged. Set the initial DD RAM address. After this command, all subsequent read or write operations to the display are to or from DD RAM. The addresses for displayed characters appear in Figure 5-3. Execution Time: 40 μs Read Busy Flag and Address Read the Busy flag (BF) to determine if an internal operation is in progress, and read the current address counter contents. BF = 1 indicates that an internal operation is in progress. The next instruction is not accepted until BF is cleared or until the current instruction is allowed the maximum time to execute. This command also returns the present value of address counter. The address counter is used for both CG RAM and DD RAM addresses. The specific context depends on the most recent Set CG RAM Address or Set DD RAM Address command issued. Execution Time: 1 μs Write Data to CG RAM or DD RAM Write data into DD RAM if the command follows a previous Set DD RAM Address command, or write data into CG RAM if the command follows a previous Set CG RAM Address command. Spartan-3E FPGA Starter Kit Board User Guide www.xilinx.com 51 UG230 (v1.2) January 20, 2011
Page 1 and 2: Spartan-3E FPGA Starter Kit Board U
Page 3 and 4: Table of Contents Preface: About Th
Page 5 and 6: R Writing Data to the Display . . .
Page 7 and 8: R UCF Location Constraints . . . .
Page 9 and 10: R About This Guide Acknowledgements
Page 11 and 12: R Introduction and Overview Chapter
Page 13 and 14: R Design Trade-Offs Design Trade-Of
Page 15 and 16: R Switches, Buttons, and Knob Slide
Page 17 and 18: R Rotary Push-Button Switch In some
Page 19 and 20: A Rotating RIGHT B Detent R Discret
Page 21 and 22: R Clock Sources Overview Chapter 3
Page 23 and 24: R Clock Period Constraints Related
Page 25 and 26: R FPGA Configuration Options Chapte
Page 27 and 28: R Configuration Mode Jumpers The co
Page 29 and 30: R Programming the FPGA, CPLD, or Pl
Page 41 and 42: R Related Resources Figure 4-26: PR
Page 43 and 44: R Character LCD Screen Overview Cha
Page 45 and 46: R UCF Location Constraints LCD Cont
Page 47 and 48: R LCD Controller The character ROM
Page 49: R Disabled If the LCD_E enable sign
Page 53 and 54: R Operation The data values on SF_D
Page 55 and 56: R VGA Display Port 1 2 3 4 5 6 11 7
Page 57 and 58: time HS R Current through the horiz
Page 59 and 60: R UCF Location Constraints Related
Page 61 and 62: R RS-232 Serial Ports Overview Chap
Page 63 and 64: R PS/2 Mouse/Keyboard Port Chapter
Page 65 and 66: ESC 76 ` ~ 0E TA B 0D Caps Lock 58
Page 67 and 68: R Voltage Supply UCF Location Const
Page 69 and 70: R Digital to Analog Converter (DAC)
Page 71 and 72: R Table 9-2: Disabled Devices on th
Page 73 and 74: R UCF Location Constraints Related
Page 75 and 76: R Analog Capture Circuit Chapter 10
Page 77 and 78: R Programmable Pre-Amplifier Finall
Page 79 and 80: R Analog to Digital Converter (ADC)
Page 81 and 82: R Disable Other Devices on the SPI
Page 83 and 84: R Chapter 11 Intel StrataFlash Para
Page 85 and 86: R Table 11-1: FPGA-to-StrataFlash C
Page 87 and 88: R Shared Connections Character LCD
Page 89 and 90: R Control Setting the FPGA Mode Sel
Page 91 and 92: R SPI Serial Flash UCF Location Con
Page 93 and 94: R Creating an SPI Serial Flash PROM
Page 95 and 96: R Configuring from SPI Flash Figure
Page 97 and 98: R Configuring from SPI Flash To gen
Page 99 and 100: R Insert Jumper on JP8 and Hold PRO
Page 101 and 102:
R Other SPI Flash Control Signals A
Page 103 and 104:
R Related Resources Related Resourc
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R DDR SDRAM 5.0V LTC3412 Chapter 13
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R Table 13-1: FPGA-to-DDR SDRAM Con
Page 109 and 110:
R Control Related Resources Figure
Page 111 and 112:
R Chapter 14 10/100 Ethernet Physic
Page 113 and 114:
R MicroBlaze Ethernet IP Cores Tabl
Page 115 and 116:
R Expansion Connectors Chapter 15 T
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R Table 15-1: Hirose 100-pin FX2 Co
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R Table 15-2: Differential I/O Pair
Page 121 and 122:
R Using Differential Outputs Hirose
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R Six-Pin Accessory Headers Header
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R Connectorless Debugging Port Land
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R XC2C64A CoolRunner-II CPLD Chapte
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R UCF Location Constraints UCF Loca
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R DS2432 1-Wire SHA-1 EEPROM UCF Lo
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Schematics R This appendix provides
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R FX2 Expansion Header, 6-pin Heade
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R Figure A-2: Schematic Sheet 2 RS-
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R Figure A-3: Schematic Sheet 4 Eth
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R Figure A-4: Schematic Sheet 5 Vol
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R FPGA Configurations Settings, Pla
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R Figure A-6: Schematic Sheet 7 FPG
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R Figure A-7: Schematic Sheet 8 FPG
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R Figure A-8: Schematic Sheet 9 Pow
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R Figure A-9: Schematic Sheet 10 XC
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R Figure A-10: Schematic Sheet 11 L
Page 155 and 156:
R Intel StrataFlash Parallel NOR Fl
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R Buttons, Switches, Rotary Encoder
Page 159 and 160:
R DDR SDRAM Series Termination and
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R Appendix B Example User Constrain
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R NET "FX2_IO" LOC = "A16" | IOSTAN
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R NET "SD_LDM" LOC = "J2" | IOSTAND
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Xilinx UG230 Spartan-3E FPGA Starter Kit Board User Guide

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