Xilinx UG230 Spartan-3E FPGA Starter Kit Board User Guide

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Chapter 5: Character LCD Screen Command Set The CG RAM address counter can either remain constant after read or write operations, or auto-increments or auto-decrements by one location, as defined by the I/D set by the Entry Mode Set command. Figure 5-5 provides an example, creating a special checkerboard character. The custom character is stored in the fourth CG RAM character location, which is displayed when a DD RAM location is 0x03. To write the custom character, the CG RAM address is first initialized using the Set CG RAM Address command. The upper three address bits point to the custom character location. The lower three address bits point to the row address for the character bitmap. The Write Data to CG RAM or DD RAM command is used to write each character bitmap row. A ‘1’ lights a bit on the display. A ‘0’ leaves the bit unlit. Only the lower five data bits are used; the upper three data bits are don’t care positions. The eighth row of bitmap data is usually left as all zeros to accommodate the cursor. Upper Nibble Lower Nibble Write Data to CG RAM or DD RAM A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Character Address Row Address Don’t Care Character Bitmap 0 1 1 0 0 0 - - - 0 1 0 1 0 0 1 1 0 0 1 - - - 1 0 1 0 1 0 1 1 0 1 0 - - - 0 1 0 1 0 0 1 1 0 1 1 - - - 1 0 1 0 1 0 1 1 1 0 0 - - - 0 1 0 1 0 0 1 1 1 0 1 - - - 1 0 1 0 1 0 1 1 1 1 0 - - - 0 1 0 1 0 0 1 1 1 1 1 - - - 0 0 0 0 0 Figure 5-5: Example Custom Checkerboard Character with Character Code 0x03 Table 5-3 summarizes the available LCD controller commands and bit definitions. Because the display is set up for 4-bit operation, each 8-bit command is sent as two 4-bit nibbles. The upper nibble is transferred first, followed by the lower nibble. Table 5-3: LCD Character Display Command Set Function LCD_RS LCD_RW Upper Nibble Lower Nibble Clear Display 0 0 0 0 0 0 0 0 0 1 Return Cursor Home 0 0 0 0 0 0 0 0 1 - Entry Mode Set 0 0 0 0 0 0 0 1 I/D S Display On/Off 0 0 0 0 0 0 1 D C B Cursor and Display Shift 0 0 0 0 0 1 S/C R/L - - 48 www.xilinx.com Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.2) January 20, 2011 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 R
R Disabled If the LCD_E enable signal is Low, all other inputs to the LCD are ignored. Clear Display LCD Controller Table 5-3: LCD Character Display Command Set (Continued) Upper Nibble Lower Nibble Function Function Set 0 0 0 0 1 0 1 0 - - Set CG RAM Address 0 0 0 1 A5 A4 A3 A2 A1 A0 Set DD RAM Address 0 0 1 A6 A5 A4 A3 A2 A1 A0 Read Busy Flag and Address 0 1 BF A6 A5 A4 A3 A2 A1 A0 Write Data to CG RAM or DD RAM 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Read Data from CG RAM or DD RAM 1 1 D7 D6 D5 D4 D3 D2 D1 D0 Clear the display and return the cursor to the home position, the top-left corner. This command writes a blank space (ASCII/ANSI character code 0x20) into all DD RAM addresses. The address counter is reset to 0, location 0x00 in DD RAM. Clears all option settings. The I/D control bit is set to 1 (increment address counter mode) in the Entry Mode Set command. Execution Time: 82 μs – 1.64 ms Return Cursor Home Return the cursor to the home position, the top-left corner. DD RAM contents are unaffected. Also returns the display being shifted to the original position, shown in Figure 5-3. The address counter is reset to 0, location 0x00 in DD RAM. The display is returned to its original status if it was shifted. The cursor or blink move to the top-left character location. Execution Time: 40 μs – 1.6 ms Entry Mode Set LCD_RS LCD_RW Sets the cursor move direction and specifies whether or not to shift the display. These operations are performed during data reads and writes. Execution Time: 40 μs Bit DB1: (I/D) Increment/Decrement 0 Auto-decrement address counter. Cursor/blink moves to left. 1 Auto-increment address counter. Cursor/blink moves to right. Spartan-3E FPGA Starter Kit Board User Guide www.xilinx.com 49 UG230 (v1.2) January 20, 2011 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Page 1 and 2: Spartan-3E FPGA Starter Kit Board U
Page 3 and 4: Table of Contents Preface: About Th
Page 5 and 6: R Writing Data to the Display . . .
Page 7 and 8: R UCF Location Constraints . . . .
Page 9 and 10: R About This Guide Acknowledgements
Page 11 and 12: R Introduction and Overview Chapter
Page 13 and 14: R Design Trade-Offs Design Trade-Of
Page 15 and 16: R Switches, Buttons, and Knob Slide
Page 17 and 18: R Rotary Push-Button Switch In some
Page 19 and 20: A Rotating RIGHT B Detent R Discret
Page 21 and 22: R Clock Sources Overview Chapter 3
Page 23 and 24: R Clock Period Constraints Related
Page 25 and 26: R FPGA Configuration Options Chapte
Page 27 and 28: R Configuration Mode Jumpers The co
Page 29 and 30: R Programming the FPGA, CPLD, or Pl
Page 41 and 42: R Related Resources Figure 4-26: PR
Page 43 and 44: R Character LCD Screen Overview Cha
Page 45 and 46: R UCF Location Constraints LCD Cont
Page 47: R LCD Controller The character ROM
Page 51 and 52: R Table 5-4: Shift Patterns Accordi
Page 53 and 54: R Operation The data values on SF_D
Page 55 and 56: R VGA Display Port 1 2 3 4 5 6 11 7
Page 57 and 58: time HS R Current through the horiz
Page 59 and 60: R UCF Location Constraints Related
Page 61 and 62: R RS-232 Serial Ports Overview Chap
Page 63 and 64: R PS/2 Mouse/Keyboard Port Chapter
Page 65 and 66: ESC 76 ` ~ 0E TA B 0D Caps Lock 58
Page 67 and 68: R Voltage Supply UCF Location Const
Page 69 and 70: R Digital to Analog Converter (DAC)
Page 71 and 72: R Table 9-2: Disabled Devices on th
Page 73 and 74: R UCF Location Constraints Related
Page 75 and 76: R Analog Capture Circuit Chapter 10
Page 77 and 78: R Programmable Pre-Amplifier Finall
Page 79 and 80: R Analog to Digital Converter (ADC)
Page 81 and 82: R Disable Other Devices on the SPI
Page 83 and 84: R Chapter 11 Intel StrataFlash Para
Page 85 and 86: R Table 11-1: FPGA-to-StrataFlash C
Page 87 and 88: R Shared Connections Character LCD
Page 89 and 90: R Control Setting the FPGA Mode Sel
Page 91 and 92: R SPI Serial Flash UCF Location Con
Page 93 and 94: R Creating an SPI Serial Flash PROM
Page 95 and 96: R Configuring from SPI Flash Figure
Page 97 and 98: R Configuring from SPI Flash To gen
Page 99 and 100:
R Insert Jumper on JP8 and Hold PRO
Page 101 and 102:
R Other SPI Flash Control Signals A
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R Related Resources Related Resourc
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R DDR SDRAM 5.0V LTC3412 Chapter 13
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R Table 13-1: FPGA-to-DDR SDRAM Con
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R Control Related Resources Figure
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R Chapter 14 10/100 Ethernet Physic
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R MicroBlaze Ethernet IP Cores Tabl
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R Expansion Connectors Chapter 15 T
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R Table 15-1: Hirose 100-pin FX2 Co
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R Table 15-2: Differential I/O Pair
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R Using Differential Outputs Hirose
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R Six-Pin Accessory Headers Header
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R Connectorless Debugging Port Land
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R XC2C64A CoolRunner-II CPLD Chapte
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R UCF Location Constraints UCF Loca
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R DS2432 1-Wire SHA-1 EEPROM UCF Lo
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Schematics R This appendix provides
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R FX2 Expansion Header, 6-pin Heade
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R Figure A-2: Schematic Sheet 2 RS-
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R Figure A-3: Schematic Sheet 4 Eth
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R Figure A-4: Schematic Sheet 5 Vol
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R FPGA Configurations Settings, Pla
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R Figure A-6: Schematic Sheet 7 FPG
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R Figure A-7: Schematic Sheet 8 FPG
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R Figure A-8: Schematic Sheet 9 Pow
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R Figure A-9: Schematic Sheet 10 XC
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R Figure A-10: Schematic Sheet 11 L
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R Intel StrataFlash Parallel NOR Fl
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R Buttons, Switches, Rotary Encoder
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R DDR SDRAM Series Termination and
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R Appendix B Example User Constrain
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R NET "FX2_IO" LOC = "A16" | IOSTAN
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R NET "SD_LDM" LOC = "J2" | IOSTAND
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Xilinx UG230 Spartan-3E FPGA Starter Kit Board User Guide

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