Xilinx UG230 Spartan-3E FPGA Starter Kit Board User Guide

More documents

Recommendations

Info

Chapter 4: FPGA Configuration Options USB-based Download/Debug Port Uses standard USB cable 16 Mbit ST Micro SPI Serial Flash Serial Peripheral Interface (SPI) mode Configuration Options PROG_B button, Platform Flash PROM, mode pins 128 Mbit Intel StrataFlash Parallel NOR Flash memory Byte Peripheral Interface (BPI) mode Figure 4-1: Spartan-3E Starter Kit FPGA Configuration Options Configuration Mode Jumper Settings (Header J30) Select between three on-board configuration sources 4 Mbit Xilinx Platform Flash PROM Configuration storage for Master Serial mode Figure 4-2: Detailed Configuration Options UG230_c4_01_022006 DONE Pin LED PROG_B Push Button Switch Lights up when FPGA successfully configured Press and release to restart configuration 64 Macrocell Xilinx XC2C64A CoolRunner CPLD Controller upper address lines in BPI mode and Platform Flash chip select (User programmable) UG230_c4_02_030906 26 www.xilinx.com Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.2) January 20, 2011 R
R Configuration Mode Jumpers The configuration mode jumpers determine which configuration mode the FPGA uses when power is first applied, or whenever the PROG button is pressed. The DONE pin LED lights when the FPGA successfully finishes configuration. Pressing the PROG button forces the FPGA to restart its configuration process. The 4 Mbit Xilinx Platform Flash PROM provides easy, JTAG-programmable configuration storage for the FPGA. The FPGA configures from the Platform Flash using Master Serial mode. The 64-macrocell XC2C64A CoolRunner-II CPLD provides additional programming capabilities and flexibility when using the BPI Up, BPI Down, or MultiBoot configuration modes and loading the FPGA from the StrataFlash parallel Flash PROM. The CPLD is userprogrammable. Configuration Mode Jumpers As shown in Table 4-1, the J30 jumper block settings control the FPGA’s configuration mode. Inserting a jumper grounds the associated mode pin. Insert or remove individual jumpers to select the FPGA’s configuration mode and associated configuration memory source. Table 4-1: Spartan-3E Configuration Mode Jumper Settings (Header J30 in Figure 4-2) Configuration Mode Mode Pins M2:M1:M0 Master Serial 0:0:0 Platform Flash PROM SPI (see Chapter 12, “SPI Serial Flash”) BPI Up (see Chapter 11, “Intel StrataFlash Parallel NOR Flash PROM”) FPGA Configuration Image Source Jumper Settings 1:1:0 SPI Serial Flash PROM starting at address 0 0:1:0 StrataFlash parallel Flash PROM, starting at address 0 and incrementing through address space. The CPLD controls address lines A[24:20] during BPI configuration. Spartan-3E FPGA Starter Kit Board User Guide www.xilinx.com 27 UG230 (v1.2) January 20, 2011 M0 M1 M2 M0 M1 M2 M0 M1 M2 J30 J30 J30
Page 1 and 2: Spartan-3E FPGA Starter Kit Board U
Page 3 and 4: Table of Contents Preface: About Th
Page 5 and 6: R Writing Data to the Display . . .
Page 7 and 8: R UCF Location Constraints . . . .
Page 9 and 10: R About This Guide Acknowledgements
Page 11 and 12: R Introduction and Overview Chapter
Page 13 and 14: R Design Trade-Offs Design Trade-Of
Page 15 and 16: R Switches, Buttons, and Knob Slide
Page 17 and 18: R Rotary Push-Button Switch In some
Page 19 and 20: A Rotating RIGHT B Detent R Discret
Page 21 and 22: R Clock Sources Overview Chapter 3
Page 23 and 24: R Clock Period Constraints Related
Page 25: R FPGA Configuration Options Chapte
Page 29 and 30: R Programming the FPGA, CPLD, or Pl
Page 41 and 42: R Related Resources Figure 4-26: PR
Page 43 and 44: R Character LCD Screen Overview Cha
Page 45 and 46: R UCF Location Constraints LCD Cont
Page 47 and 48: R LCD Controller The character ROM
Page 49 and 50: R Disabled If the LCD_E enable sign
Page 51 and 52: R Table 5-4: Shift Patterns Accordi
Page 53 and 54: R Operation The data values on SF_D
Page 55 and 56: R VGA Display Port 1 2 3 4 5 6 11 7
Page 57 and 58: time HS R Current through the horiz
Page 59 and 60: R UCF Location Constraints Related
Page 61 and 62: R RS-232 Serial Ports Overview Chap
Page 63 and 64: R PS/2 Mouse/Keyboard Port Chapter
Page 65 and 66: ESC 76 ` ~ 0E TA B 0D Caps Lock 58
Page 67 and 68: R Voltage Supply UCF Location Const
Page 69 and 70: R Digital to Analog Converter (DAC)
Page 71 and 72: R Table 9-2: Disabled Devices on th
Page 73 and 74: R UCF Location Constraints Related
Page 75 and 76: R Analog Capture Circuit Chapter 10
Page 77 and 78:
R Programmable Pre-Amplifier Finall
Page 79 and 80:
R Analog to Digital Converter (ADC)
Page 81 and 82:
R Disable Other Devices on the SPI
Page 83 and 84:
R Chapter 11 Intel StrataFlash Para
Page 85 and 86:
R Table 11-1: FPGA-to-StrataFlash C
Page 87 and 88:
R Shared Connections Character LCD
Page 89 and 90:
R Control Setting the FPGA Mode Sel
Page 91 and 92:
R SPI Serial Flash UCF Location Con
Page 93 and 94:
R Creating an SPI Serial Flash PROM
Page 95 and 96:
R Configuring from SPI Flash Figure
Page 97 and 98:
R Configuring from SPI Flash To gen
Page 99 and 100:
R Insert Jumper on JP8 and Hold PRO
Page 101 and 102:
R Other SPI Flash Control Signals A
Page 103 and 104:
R Related Resources Related Resourc
Page 105 and 106:
R DDR SDRAM 5.0V LTC3412 Chapter 13
Page 107 and 108:
R Table 13-1: FPGA-to-DDR SDRAM Con
Page 109 and 110:
R Control Related Resources Figure
Page 111 and 112:
R Chapter 14 10/100 Ethernet Physic
Page 113 and 114:
R MicroBlaze Ethernet IP Cores Tabl
Page 115 and 116:
R Expansion Connectors Chapter 15 T
Page 117 and 118:
R Table 15-1: Hirose 100-pin FX2 Co
Page 119 and 120:
R Table 15-2: Differential I/O Pair
Page 121 and 122:
R Using Differential Outputs Hirose
Page 123 and 124:
R Six-Pin Accessory Headers Header
Page 125 and 126:
R Connectorless Debugging Port Land
Page 127 and 128:
R XC2C64A CoolRunner-II CPLD Chapte
Page 129 and 130:
R UCF Location Constraints UCF Loca
Page 131 and 132:
R DS2432 1-Wire SHA-1 EEPROM UCF Lo
Page 133 and 134:
Schematics R This appendix provides
Page 135 and 136:
R FX2 Expansion Header, 6-pin Heade
Page 137 and 138:
R Figure A-2: Schematic Sheet 2 RS-
Page 139 and 140:
R Figure A-3: Schematic Sheet 4 Eth
Page 141 and 142:
R Figure A-4: Schematic Sheet 5 Vol
Page 143 and 144:
R FPGA Configurations Settings, Pla
Page 145 and 146:
R Figure A-6: Schematic Sheet 7 FPG
Page 147 and 148:
R Figure A-7: Schematic Sheet 8 FPG
Page 149 and 150:
R Figure A-8: Schematic Sheet 9 Pow
Page 151 and 152:
R Figure A-9: Schematic Sheet 10 XC
Page 153 and 154:
R Figure A-10: Schematic Sheet 11 L
Page 155 and 156:
R Intel StrataFlash Parallel NOR Fl
Page 157 and 158:
R Buttons, Switches, Rotary Encoder
Page 159 and 160:
R DDR SDRAM Series Termination and
Page 161 and 162:
R Appendix B Example User Constrain
Page 163 and 164:
R NET "FX2_IO" LOC = "A16" | IOSTAN
Page 165 and 166:
R NET "SD_LDM" LOC = "J2" | IOSTAND
show all

Xilinx UG230 Spartan-3E FPGA Starter Kit Board User Guide

Create successful ePaper yourself

Delete template?

Save as template?