Xilinx UG230 Spartan-3E FPGA Starter Kit Board User Guide

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Chapter 11: Intel StrataFlash Parallel NOR Flash PROM StrataFlash Connections Stores MicroBlaze processor code in the StrataFlash device and shadows the code into the DDR memory before executing the code. Stores non-volatile data from the FPGA. Table 11-1 shows the connections between the FPGA and the StrataFlash device. Although the XC3S500E FPGA only requires just slightly over 2 Mbits per configuration image, the FPGA-to-StrataFlash interface on the board support up to a 256 Mbit StrataFlash. The Spartan-3E FPGA Starter Kit board ships with a 128 Mbit device. Address line SF_A24 is not used. In general, the StrataFlash device connects to the XC3S500E to support Byte Peripheral Interface (BPI) configuration. The upper four address bits from the FPGA, A[23:19] do not connect directly to the StrataFlash device. Instead, the XC2C64 CPLD controls the pins during configuration. As described in Table 11-1 and Shared Connections, some of the StrataFlash connections are shared with other components on the board. 84 www.xilinx.com Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.2) January 20, 2011 R
R Table 11-1: FPGA-to-StrataFlash Connections Category Address StrataFlash Signal Name FPGA Pin Number StrataFlash Connections Function SF_A24 A11 Shared with XC2C64A CPLD. The CPLD SF_A23 N11 actively drives these pins during FPGA configuration, as described in Chapter 16, SF_A22 V12 “XC2C64A CoolRunner-II CPLD”. Also SF_A21 V13 connects to FPGA user-I/O pins. SF_A24 is the same as FX2 connector signal FX2_IO. SF_A20 T12 SF_A19 V15 Connects to FPGA pins A[19:0] to support the SF_A18 U15 BPI configuration. SF_A17 T16 SF_A16 U18 SF_A15 T17 SF_A14 R18 SF_A13 T18 SF_A12 L16 SF_A11 L15 SF_A10 K13 SF_A9 K12 SF_A8 K15 SF_A7 K14 SF_A6 J17 SF_A5 J16 SF_A4 J15 SF_A3 J14 SF_A2 J12 SF_A1 J13 SF_A0 H17 Spartan-3E FPGA Starter Kit Board User Guide www.xilinx.com 85 UG230 (v1.2) January 20, 2011
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Spartan-3E FPGA Starter Kit Board U
Page 3 and 4:
Table of Contents Preface: About Th
Page 5 and 6:
R Writing Data to the Display . . .
Page 7 and 8:
R UCF Location Constraints . . . .
Page 9 and 10:
R About This Guide Acknowledgements
Page 11 and 12:
R Introduction and Overview Chapter
Page 13 and 14:
R Design Trade-Offs Design Trade-Of
Page 15 and 16:
R Switches, Buttons, and Knob Slide
Page 17 and 18:
R Rotary Push-Button Switch In some
Page 19 and 20:
A Rotating RIGHT B Detent R Discret
Page 21 and 22:
R Clock Sources Overview Chapter 3
Page 23 and 24:
R Clock Period Constraints Related
Page 25 and 26:
R FPGA Configuration Options Chapte
Page 27 and 28:
R Configuration Mode Jumpers The co
Page 29 and 30:
R Programming the FPGA, CPLD, or Pl
Page 31 and 32:
R Programming the FPGA, CPLD, or Pl
Page 33 and 34: R Programming the FPGA, CPLD, or Pl
Page 41 and 42: R Related Resources Figure 4-26: PR
Page 43 and 44: R Character LCD Screen Overview Cha
Page 45 and 46: R UCF Location Constraints LCD Cont
Page 47 and 48: R LCD Controller The character ROM
Page 49 and 50: R Disabled If the LCD_E enable sign
Page 51 and 52: R Table 5-4: Shift Patterns Accordi
Page 53 and 54: R Operation The data values on SF_D
Page 55 and 56: R VGA Display Port 1 2 3 4 5 6 11 7
Page 57 and 58: time HS R Current through the horiz
Page 59 and 60: R UCF Location Constraints Related
Page 61 and 62: R RS-232 Serial Ports Overview Chap
Page 63 and 64: R PS/2 Mouse/Keyboard Port Chapter
Page 65 and 66: ESC 76 ` ~ 0E TA B 0D Caps Lock 58
Page 67 and 68: R Voltage Supply UCF Location Const
Page 69 and 70: R Digital to Analog Converter (DAC)
Page 71 and 72: R Table 9-2: Disabled Devices on th
Page 73 and 74: R UCF Location Constraints Related
Page 75 and 76: R Analog Capture Circuit Chapter 10
Page 77 and 78: R Programmable Pre-Amplifier Finall
Page 79 and 80: R Analog to Digital Converter (ADC)
Page 81 and 82: R Disable Other Devices on the SPI
Page 83: R Chapter 11 Intel StrataFlash Para
Page 87 and 88: R Shared Connections Character LCD
Page 89 and 90: R Control Setting the FPGA Mode Sel
Page 91 and 92: R SPI Serial Flash UCF Location Con
Page 93 and 94: R Creating an SPI Serial Flash PROM
Page 95 and 96: R Configuring from SPI Flash Figure
Page 97 and 98: R Configuring from SPI Flash To gen
Page 99 and 100: R Insert Jumper on JP8 and Hold PRO
Page 101 and 102: R Other SPI Flash Control Signals A
Page 103 and 104: R Related Resources Related Resourc
Page 105 and 106: R DDR SDRAM 5.0V LTC3412 Chapter 13
Page 107 and 108: R Table 13-1: FPGA-to-DDR SDRAM Con
Page 109 and 110: R Control Related Resources Figure
Page 111 and 112: R Chapter 14 10/100 Ethernet Physic
Page 113 and 114: R MicroBlaze Ethernet IP Cores Tabl
Page 115 and 116: R Expansion Connectors Chapter 15 T
Page 117 and 118: R Table 15-1: Hirose 100-pin FX2 Co
Page 119 and 120: R Table 15-2: Differential I/O Pair
Page 121 and 122: R Using Differential Outputs Hirose
Page 123 and 124: R Six-Pin Accessory Headers Header
Page 125 and 126: R Connectorless Debugging Port Land
Page 127 and 128: R XC2C64A CoolRunner-II CPLD Chapte
Page 129 and 130: R UCF Location Constraints UCF Loca
Page 131 and 132: R DS2432 1-Wire SHA-1 EEPROM UCF Lo
Page 133 and 134: Schematics R This appendix provides
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R FX2 Expansion Header, 6-pin Heade
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R Figure A-2: Schematic Sheet 2 RS-
Page 139 and 140:
R Figure A-3: Schematic Sheet 4 Eth
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R Figure A-4: Schematic Sheet 5 Vol
Page 143 and 144:
R FPGA Configurations Settings, Pla
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R Figure A-6: Schematic Sheet 7 FPG
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R Figure A-7: Schematic Sheet 8 FPG
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R Figure A-8: Schematic Sheet 9 Pow
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R Figure A-9: Schematic Sheet 10 XC
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R Figure A-10: Schematic Sheet 11 L
Page 155 and 156:
R Intel StrataFlash Parallel NOR Fl
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R Buttons, Switches, Rotary Encoder
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R DDR SDRAM Series Termination and
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R Appendix B Example User Constrain
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R NET "FX2_IO" LOC = "A16" | IOSTAN
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R NET "SD_LDM" LOC = "J2" | IOSTAND
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Xilinx UG230 Spartan-3E FPGA Starter Kit Board User Guide

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