Xilinx UG230 Spartan-3E FPGA Starter Kit Board User Guide

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Chapter 10: Analog Capture Circuit Spartan-3E FPGA Master AD_CONV SPI_SCK SPI_MISO AD_CONV SPI_SCK SPI_MISO SPI_MISO AD_CONV SPI_SCK Sample point 4ns min 3ns D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 Z Channel 1 Z Channel 0 Z Converted data is presented with a latency of one sample. The sampled analog value is converted to digital data 32 SPI_SCK cycles after asserting AD_CONV. The converted values is then presented after the next AD_CONV pulse. Sample point Channel 0 Channel 1 Channel 0 13 0 13 0 13 Figure 10-7 shows detailed transaction timing. The AD_CONV signal is not a traditional SPI slave select enable. Be sure to provide enough SPI_SCK clock cycles so that the ADC leaves the SPI_MISO signal in the high-impedance state. Otherwise, the ADC blocks communication to the other SPI peripherals. As shown in Figure 10-6, use a 34-cycle communications sequence. The ADC 3-states its data output for two clock cycles before and after each 14-bit data transfer. UCF Location Constraints Slave: LTC1407A-1 A/D Converter Figure 10-6: Analog-to-Digital Conversion Interface 1 2 3 High-Z AD_CONV SPI_SCK SPI_MISO Channel 1 3 30 Channel 0 31 13 12 11 2 1 0 Figure 10-7: Detailed SPI Timing to ADC UG230_c10_05_030306 Figure 10-8 provides the User Constraint File (UCF) constraints for the amplifier interface, including the I/O pin assignment and I/O standard used. 80 www.xilinx.com Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.2) January 20, 2011 4 8ns 32 19.6ns min 5 6 33 6ns 45ns min 34 High-Z The A/D converter sets its SDO output line to high impedance after 33 SPI_SCK clock cycles UG230_c10_06_022306 NET "AD_CONV" LOC = "P11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ; NET "SPI_SCK" LOC = "U16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; NET "SPI_MISO" LOC = "N10" | IOSTANDARD = LVCMOS33 ; Figure 10-8: UCF Location Constraints for the ADC Interface R
R Disable Other Devices on the SPI Bus to Avoid Contention Disable Other Devices on the SPI Bus to Avoid Contention Connecting Analog Inputs Related Resources The SPI bus signals are shared by other devices on the board. It is vital that other devices are disabled when the FPGA communicates with the AMP or ADC to avoid bus contention. Table 10-4 provides the signals and logic values required to disable the other devices. Although the StrataFlash PROM is a parallel device, its least-significant data bit is shared with the SPI_MISO signal. The Platform Flash PROM is only potentially enabled if the FPGA is set up for Master Serial mode configuration. Table 10-4: Disable Other Devices on SPI Bus Signal Disabled Device Disable Value SPI_SS_B SPI Serial Flash 1 AMP_CS Programmable Pre-Amplifier 1 DAC_CS DAC 1 SF_CE0 StrataFlash Parallel Flash PROM 1 FPGA_INIT_B Platform Flash PROM 0 Connect AC signals to VINA or VINB via a DC blocking capacitor. Amplifier and A/D Converter Control for the Spartan-3E Starter Kit (Reference Design) http://www.xilinx.com/s3estarter Xilinx PicoBlaze Soft Processor http://www.xilinx.com/picoblaze LTC6912 Dual Programmable Gain Amplifiers with Serial Digital Interface http://www.linear.com/pc/downloadDocument.do?navId=H0,C1,C1154,C1009,C1121,P7596,D5359 LTC1407A-1 Serial 14-bit Simultaneous Sampling ADCs with Shutdown http://www.linear.com/pc/downloadDocument.do?navId=H0,C1,C1155,C1001,C1158,P2420,D1295 Spartan-3E FPGA Starter Kit Board User Guide www.xilinx.com 81 UG230 (v1.2) January 20, 2011
Page 1 and 2:
Spartan-3E FPGA Starter Kit Board U
Page 3 and 4:
Table of Contents Preface: About Th
Page 5 and 6:
R Writing Data to the Display . . .
Page 7 and 8:
R UCF Location Constraints . . . .
Page 9 and 10:
R About This Guide Acknowledgements
Page 11 and 12:
R Introduction and Overview Chapter
Page 13 and 14:
R Design Trade-Offs Design Trade-Of
Page 15 and 16:
R Switches, Buttons, and Knob Slide
Page 17 and 18:
R Rotary Push-Button Switch In some
Page 19 and 20:
A Rotating RIGHT B Detent R Discret
Page 21 and 22:
R Clock Sources Overview Chapter 3
Page 23 and 24:
R Clock Period Constraints Related
Page 25 and 26:
R FPGA Configuration Options Chapte
Page 27 and 28:
R Configuration Mode Jumpers The co
Page 29 and 30: R Programming the FPGA, CPLD, or Pl
Page 41 and 42: R Related Resources Figure 4-26: PR
Page 43 and 44: R Character LCD Screen Overview Cha
Page 45 and 46: R UCF Location Constraints LCD Cont
Page 47 and 48: R LCD Controller The character ROM
Page 49 and 50: R Disabled If the LCD_E enable sign
Page 51 and 52: R Table 5-4: Shift Patterns Accordi
Page 53 and 54: R Operation The data values on SF_D
Page 55 and 56: R VGA Display Port 1 2 3 4 5 6 11 7
Page 57 and 58: time HS R Current through the horiz
Page 59 and 60: R UCF Location Constraints Related
Page 61 and 62: R RS-232 Serial Ports Overview Chap
Page 63 and 64: R PS/2 Mouse/Keyboard Port Chapter
Page 65 and 66: ESC 76 ` ~ 0E TA B 0D Caps Lock 58
Page 67 and 68: R Voltage Supply UCF Location Const
Page 69 and 70: R Digital to Analog Converter (DAC)
Page 71 and 72: R Table 9-2: Disabled Devices on th
Page 73 and 74: R UCF Location Constraints Related
Page 75 and 76: R Analog Capture Circuit Chapter 10
Page 77 and 78: R Programmable Pre-Amplifier Finall
Page 79: R Analog to Digital Converter (ADC)
Page 83 and 84: R Chapter 11 Intel StrataFlash Para
Page 85 and 86: R Table 11-1: FPGA-to-StrataFlash C
Page 87 and 88: R Shared Connections Character LCD
Page 89 and 90: R Control Setting the FPGA Mode Sel
Page 91 and 92: R SPI Serial Flash UCF Location Con
Page 93 and 94: R Creating an SPI Serial Flash PROM
Page 95 and 96: R Configuring from SPI Flash Figure
Page 97 and 98: R Configuring from SPI Flash To gen
Page 99 and 100: R Insert Jumper on JP8 and Hold PRO
Page 101 and 102: R Other SPI Flash Control Signals A
Page 103 and 104: R Related Resources Related Resourc
Page 105 and 106: R DDR SDRAM 5.0V LTC3412 Chapter 13
Page 107 and 108: R Table 13-1: FPGA-to-DDR SDRAM Con
Page 109 and 110: R Control Related Resources Figure
Page 111 and 112: R Chapter 14 10/100 Ethernet Physic
Page 113 and 114: R MicroBlaze Ethernet IP Cores Tabl
Page 115 and 116: R Expansion Connectors Chapter 15 T
Page 117 and 118: R Table 15-1: Hirose 100-pin FX2 Co
Page 119 and 120: R Table 15-2: Differential I/O Pair
Page 121 and 122: R Using Differential Outputs Hirose
Page 123 and 124: R Six-Pin Accessory Headers Header
Page 125 and 126: R Connectorless Debugging Port Land
Page 127 and 128: R XC2C64A CoolRunner-II CPLD Chapte
Page 129 and 130: R UCF Location Constraints UCF Loca
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R DS2432 1-Wire SHA-1 EEPROM UCF Lo
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Schematics R This appendix provides
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R FX2 Expansion Header, 6-pin Heade
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R Figure A-2: Schematic Sheet 2 RS-
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R Figure A-3: Schematic Sheet 4 Eth
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R Figure A-4: Schematic Sheet 5 Vol
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R FPGA Configurations Settings, Pla
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R Figure A-6: Schematic Sheet 7 FPG
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R Figure A-7: Schematic Sheet 8 FPG
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R Figure A-8: Schematic Sheet 9 Pow
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R Figure A-9: Schematic Sheet 10 XC
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R Figure A-10: Schematic Sheet 11 L
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R Intel StrataFlash Parallel NOR Fl
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R Buttons, Switches, Rotary Encoder
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R DDR SDRAM Series Termination and
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R Appendix B Example User Constrain
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R NET "FX2_IO" LOC = "A16" | IOSTAN
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R NET "SD_LDM" LOC = "J2" | IOSTAND
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Xilinx UG230 Spartan-3E FPGA Starter Kit Board User Guide

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