Xilinx UG230 Spartan-3E FPGA Starter Kit Board User Guide

Chapter 15: Expansion Connectors
Spartan-3E FPGA
(See Table)
(See Table)
(C3)
(C15)
(E10)
(D10)
(D9)
Figure 15-2: FPGA Connections to the Hirose 100-pin Edge Connector
Three signals are reserved primarily as clock signals between the board and FX2 connector,
although all three connect to full I/O pins.
Voltage Supplies to the Connector
FX2_IO
FX2_IP
FX2_IO
FX2_IP
FX2_CLKIN
FX2_CLKOUT
FX2_CLKIO
Bank 0 Supply
(JP9)
2.5V
3.3V
The Spartan-3E Starter Kit board provides power to the Hirose 100-pin FX connector and
any attached board via two supplies (see Figure 15-2). The 5.0V supply provides a voltage
source for any 5V logic on the attached board or alternately provides power to any voltage
regulators on the attached board.
A separate supply provides the same voltage at that applied to the FPGA’s I/O Bank 0. All
FPGA I/Os that interface to the Hirose connector are in Bank 0. The I/O Bank 0 supply is
3.3V by default. However, the voltage level can be changed to 2.5V using jumper JP9. Some
FPGA I/O standards—especially the differential standards such as RSDS and LVDS—
require a 2.5V output supply voltage.
To support high-speed signals across the connector, a majority of pins on the B-side of the
FX2 connector are tied to GND.
Connector Pinout and FPGA Connections
Hirose 100-pin Expansion
Connector (J3)
Table 15-1 shows the pinout for the Hirose 100-pin FX2 connector and the associated FPGA
pin connections. The FX2 connect has two rows of connectors, both with 50 connections
each, shown in the table using light yellow shading.
Table 15-1 also highlights the shared connections to the eight discrete LEDs, the three 6-pin
Accessory Headers (J1, J2, and J4), and the connectorless debugging header (J6).
116 www.xilinx.com Spartan-3E FPGA Starter Kit Board User Guide
UG230 (v1.2) January 20, 2011
5.0V
GND
(See Table)
(See Table)
(A.44)
(A.45)
(B.46)
(A.47)
(B.48)
UG230_c12_02_022406
R