Xilinx UG230 Spartan-3E FPGA Starter Kit Board User Guide
Xilinx UG230 Spartan-3E FPGA Starter Kit Board User Guide
Xilinx UG230 Spartan-3E FPGA Starter Kit Board User Guide
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Appendix B: Example <strong>User</strong> Constraints File (UCF)<br />
NET "LED" LOC = "E9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;<br />
NET "LED" LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;<br />
# ==== PS/2 Mouse/Keyboard Port (PS2) ====<br />
NET "PS2_CLK" LOC = "G14" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;<br />
NET "PS2_DATA" LOC = "G13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;<br />
# ==== Rotary Pushbutton Switch (ROT) ====<br />
NET "ROT_A" LOC = "K18" | IOSTANDARD = LVTTL | PULLUP ;<br />
NET "ROT_B" LOC = "G18" | IOSTANDARD = LVTTL | PULLUP ;<br />
NET "ROT_CENTER" LOC = "V16" | IOSTANDARD = LVTTL | PULLDOWN ;<br />
# ==== RS-232 Serial Ports (RS232) ====<br />
NET "RS232_DCE_RXD" LOC = "R7" | IOSTANDARD = LVTTL ;<br />
NET "RS232_DCE_TXD" LOC = "M14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;<br />
NET "RS232_DTE_RXD" LOC = "U8" | IOSTANDARD = LVTTL ;<br />
NET "RS232_DTE_TXD" LOC = "M13" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;<br />
# ==== DDR SDRAM (SD) ==== (I/O Bank 3, VCCO=2.5V)<br />
NET "SD_A" LOC = "T1" | IOSTANDARD = SSTL2_I ;<br />
NET "SD_A" LOC = "R3" | IOSTANDARD = SSTL2_I ;<br />
NET "SD_A" LOC = "R2" | IOSTANDARD = SSTL2_I ;<br />
NET "SD_A" LOC = "P1" | IOSTANDARD = SSTL2_I ;<br />
NET "SD_A" LOC = "F4" | IOSTANDARD = SSTL2_I ;<br />
NET "SD_A" LOC = "H4" | IOSTANDARD = SSTL2_I ;<br />
NET "SD_A" LOC = "H3" | IOSTANDARD = SSTL2_I ;<br />
NET "SD_A" LOC = "H1" | IOSTANDARD = SSTL2_I ;<br />
NET "SD_A" LOC = "H2" | IOSTANDARD = SSTL2_I ;<br />
NET "SD_A" LOC = "N4" | IOSTANDARD = SSTL2_I ;<br />
NET "SD_A" LOC = "T2" | IOSTANDARD = SSTL2_I ;<br />
NET "SD_A" LOC = "N5" | IOSTANDARD = SSTL2_I ;<br />
NET "SD_A" LOC = "P2" | IOSTANDARD = SSTL2_I ;<br />
NET "SD_BA" LOC = "K5" | IOSTANDARD = SSTL2_I ;<br />
NET "SD_BA" LOC = "K6" | IOSTANDARD = SSTL2_I ;<br />
NET "SD_CAS" LOC = "C2" | IOSTANDARD = SSTL2_I ;<br />
NET "SD_CK_N" LOC = "J4" | IOSTANDARD = SSTL2_I ;<br />
NET "SD_CK_P" LOC = "J5" | IOSTANDARD = SSTL2_I ;<br />
NET "SD_CKE" LOC = "K3" | IOSTANDARD = SSTL2_I ;<br />
NET "SD_CS" LOC = "K4" | IOSTANDARD = SSTL2_I ;<br />
NET "SD_DQ" LOC = "L2" | IOSTANDARD = SSTL2_I ;<br />
NET "SD_DQ" LOC = "L1" | IOSTANDARD = SSTL2_I ;<br />
NET "SD_DQ" LOC = "L3" | IOSTANDARD = SSTL2_I ;<br />
NET "SD_DQ" LOC = "L4" | IOSTANDARD = SSTL2_I ;<br />
NET "SD_DQ" LOC = "M3" | IOSTANDARD = SSTL2_I ;<br />
NET "SD_DQ" LOC = "M4" | IOSTANDARD = SSTL2_I ;<br />
NET "SD_DQ" LOC = "M5" | IOSTANDARD = SSTL2_I ;<br />
NET "SD_DQ" LOC = "M6" | IOSTANDARD = SSTL2_I ;<br />
NET "SD_DQ" LOC = "E2" | IOSTANDARD = SSTL2_I ;<br />
NET "SD_DQ" LOC = "E1" | IOSTANDARD = SSTL2_I ;<br />
NET "SD_DQ" LOC = "F1" | IOSTANDARD = SSTL2_I ;<br />
NET "SD_DQ" LOC = "F2" | IOSTANDARD = SSTL2_I ;<br />
NET "SD_DQ" LOC = "G6" | IOSTANDARD = SSTL2_I ;<br />
NET "SD_DQ" LOC = "G5" | IOSTANDARD = SSTL2_I ;<br />
NET "SD_DQ" LOC = "H6" | IOSTANDARD = SSTL2_I ;<br />
NET "SD_DQ" LOC = "H5" | IOSTANDARD = SSTL2_I ;<br />
164 www.xilinx.com <strong>Spartan</strong>-<strong>3E</strong> <strong>FPGA</strong> <strong>Starter</strong> <strong>Kit</strong> <strong>Board</strong> <strong>User</strong> <strong>Guide</strong><br />
<strong>UG230</strong> (v1.2) January 20, 2011<br />
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