Xilinx UG230 Spartan-3E FPGA Starter Kit Board User Guide

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Chapter 15: Expansion Connectors Spartan-3E FPGA (See Table) (See Table) (C3) (C15) (E10) (D10) (D9) Figure 15-2: FPGA Connections to the Hirose 100-pin Edge Connector Three signals are reserved primarily as clock signals between the board and FX2 connector, although all three connect to full I/O pins. Voltage Supplies to the Connector FX2_IO FX2_IP FX2_IO FX2_IP FX2_CLKIN FX2_CLKOUT FX2_CLKIO Bank 0 Supply (JP9) 2.5V 3.3V The Spartan-3E Starter Kit board provides power to the Hirose 100-pin FX connector and any attached board via two supplies (see Figure 15-2). The 5.0V supply provides a voltage source for any 5V logic on the attached board or alternately provides power to any voltage regulators on the attached board. A separate supply provides the same voltage at that applied to the FPGA’s I/O Bank 0. All FPGA I/Os that interface to the Hirose connector are in Bank 0. The I/O Bank 0 supply is 3.3V by default. However, the voltage level can be changed to 2.5V using jumper JP9. Some FPGA I/O standards—especially the differential standards such as RSDS and LVDS— require a 2.5V output supply voltage. To support high-speed signals across the connector, a majority of pins on the B-side of the FX2 connector are tied to GND. Connector Pinout and FPGA Connections Hirose 100-pin Expansion Connector (J3) Table 15-1 shows the pinout for the Hirose 100-pin FX2 connector and the associated FPGA pin connections. The FX2 connect has two rows of connectors, both with 50 connections each, shown in the table using light yellow shading. Table 15-1 also highlights the shared connections to the eight discrete LEDs, the three 6-pin Accessory Headers (J1, J2, and J4), and the connectorless debugging header (J6). 116 www.xilinx.com Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.2) January 20, 2011 5.0V GND (See Table) (See Table) (A.44) (A.45) (B.46) (A.47) (B.48) UG230_c12_02_022406 R
R Table 15-1: Hirose 100-pin FX2 Connector Pinout and FPGA Connections (J3) Signal Name FPGA Pin Shared Header Connections FX2 Connector LED J1 J2 JP4 J6 Hirose 100-pin FX2 Edge Connector (J3) FPGA Pin Signal Name Spartan-3E FPGA Starter Kit Board User Guide www.xilinx.com 117 UG230 (v1.2) January 20, 2011 A (top) B (bottom) VCCO_0 1 1 SHIELD VCCO_0 2 2 GND GND TMS_B 3 3 TDO_XC2C JTSEL 4 4 TCK_B TDO_FX2 5 5 GND GND FX2_IO1 B4 ◆ ◆ 6 6 GND GND FX2_IO2 A4 ◆ ◆ 7 7 GND GND FX2_IO3 D5 ◆ ◆ 8 8 GND GND FX2_IO4 C5 ◆ ◆ 9 9 GND GND FX2_IO5 A6 ◆ ◆ 10 10 GND GND FX2_IO6 B6 ◆ ◆ 11 11 GND GND FX2_IO7 E7 ◆ ◆ 12 12 GND GND FX2_IO8 F7 ◆ ◆ 13 13 GND GND FX2_IO9 D7 ◆ ◆ 14 14 GND GND FX2_IO10 C7 ◆ ◆ 15 15 GND GND FX2_IO11 F8 ◆ ◆ 16 16 GND GND FX2_IO12 E8 ◆ ◆ 17 17 GND GND FX2_IO13 F9 LD7 ◆ 18 18 GND GND FX2_IO14 E9 LD6 ◆ 19 19 GND GND FX2_IO15 D11 LD5 ◆ 20 20 GND GND FX2_IO16 C11 LD4 ◆ 21 21 GND GND FX2_IO17 F11 LD3 ◆ 22 22 GND GND FX2_IO18 E11 LD2 ◆ 23 23 GND GND FX2_IO19 E12 LD1 24 24 GND GND FX2_IO20 F12 LD0 25 25 GND GND FX2_IO21 A13 26 26 GND GND FX2_IO22 B13 27 27 GND GND FX2_IO23 A14 28 28 GND GND FX2_IO24 B14 29 29 GND GND FX2_IO25 C14 30 30 GND GND FX2_IO26 D14 31 31 GND GND FX2_IO27 A16 32 32 GND GND FX2_IO28 B16 33 33 GND GND FX2_IO29 E13 34 34 GND GND
Page 1 and 2:
Spartan-3E FPGA Starter Kit Board U
Page 3 and 4:
Table of Contents Preface: About Th
Page 5 and 6:
R Writing Data to the Display . . .
Page 7 and 8:
R UCF Location Constraints . . . .
Page 9 and 10:
R About This Guide Acknowledgements
Page 11 and 12:
R Introduction and Overview Chapter
Page 13 and 14:
R Design Trade-Offs Design Trade-Of
Page 15 and 16:
R Switches, Buttons, and Knob Slide
Page 17 and 18:
R Rotary Push-Button Switch In some
Page 19 and 20:
A Rotating RIGHT B Detent R Discret
Page 21 and 22:
R Clock Sources Overview Chapter 3
Page 23 and 24:
R Clock Period Constraints Related
Page 25 and 26:
R FPGA Configuration Options Chapte
Page 27 and 28:
R Configuration Mode Jumpers The co
Page 29 and 30:
R Programming the FPGA, CPLD, or Pl
Page 31 and 32:
Page 33 and 34:
Page 35 and 36:
Page 37 and 38:
Page 39 and 40:
Page 41 and 42:
R Related Resources Figure 4-26: PR
Page 43 and 44:
R Character LCD Screen Overview Cha
Page 45 and 46:
R UCF Location Constraints LCD Cont
Page 47 and 48:
R LCD Controller The character ROM
Page 49 and 50:
R Disabled If the LCD_E enable sign
Page 51 and 52:
R Table 5-4: Shift Patterns Accordi
Page 53 and 54:
R Operation The data values on SF_D
Page 55 and 56:
R VGA Display Port 1 2 3 4 5 6 11 7
Page 57 and 58:
time HS R Current through the horiz
Page 59 and 60:
R UCF Location Constraints Related
Page 61 and 62:
R RS-232 Serial Ports Overview Chap
Page 63 and 64:
R PS/2 Mouse/Keyboard Port Chapter
Page 65 and 66: ESC 76 ` ~ 0E TA B 0D Caps Lock 58
Page 67 and 68: R Voltage Supply UCF Location Const
Page 69 and 70: R Digital to Analog Converter (DAC)
Page 71 and 72: R Table 9-2: Disabled Devices on th
Page 73 and 74: R UCF Location Constraints Related
Page 75 and 76: R Analog Capture Circuit Chapter 10
Page 77 and 78: R Programmable Pre-Amplifier Finall
Page 79 and 80: R Analog to Digital Converter (ADC)
Page 81 and 82: R Disable Other Devices on the SPI
Page 83 and 84: R Chapter 11 Intel StrataFlash Para
Page 85 and 86: R Table 11-1: FPGA-to-StrataFlash C
Page 87 and 88: R Shared Connections Character LCD
Page 89 and 90: R Control Setting the FPGA Mode Sel
Page 91 and 92: R SPI Serial Flash UCF Location Con
Page 93 and 94: R Creating an SPI Serial Flash PROM
Page 95 and 96: R Configuring from SPI Flash Figure
Page 97 and 98: R Configuring from SPI Flash To gen
Page 99 and 100: R Insert Jumper on JP8 and Hold PRO
Page 101 and 102: R Other SPI Flash Control Signals A
Page 103 and 104: R Related Resources Related Resourc
Page 105 and 106: R DDR SDRAM 5.0V LTC3412 Chapter 13
Page 107 and 108: R Table 13-1: FPGA-to-DDR SDRAM Con
Page 109 and 110: R Control Related Resources Figure
Page 111 and 112: R Chapter 14 10/100 Ethernet Physic
Page 113 and 114: R MicroBlaze Ethernet IP Cores Tabl
Page 115: R Expansion Connectors Chapter 15 T
Page 119 and 120: R Table 15-2: Differential I/O Pair
Page 121 and 122: R Using Differential Outputs Hirose
Page 123 and 124: R Six-Pin Accessory Headers Header
Page 125 and 126: R Connectorless Debugging Port Land
Page 127 and 128: R XC2C64A CoolRunner-II CPLD Chapte
Page 129 and 130: R UCF Location Constraints UCF Loca
Page 131 and 132: R DS2432 1-Wire SHA-1 EEPROM UCF Lo
Page 133 and 134: Schematics R This appendix provides
Page 135 and 136: R FX2 Expansion Header, 6-pin Heade
Page 137 and 138: R Figure A-2: Schematic Sheet 2 RS-
Page 139 and 140: R Figure A-3: Schematic Sheet 4 Eth
Page 141 and 142: R Figure A-4: Schematic Sheet 5 Vol
Page 143 and 144: R FPGA Configurations Settings, Pla
Page 145 and 146: R Figure A-6: Schematic Sheet 7 FPG
Page 147 and 148: R Figure A-7: Schematic Sheet 8 FPG
Page 149 and 150: R Figure A-8: Schematic Sheet 9 Pow
Page 151 and 152: R Figure A-9: Schematic Sheet 10 XC
Page 153 and 154: R Figure A-10: Schematic Sheet 11 L
Page 155 and 156: R Intel StrataFlash Parallel NOR Fl
Page 157 and 158: R Buttons, Switches, Rotary Encoder
Page 159 and 160: R DDR SDRAM Series Termination and
Page 161 and 162: R Appendix B Example User Constrain
Page 163 and 164: R NET "FX2_IO" LOC = "A16" | IOSTAN
Page 165 and 166: R NET "SD_LDM" LOC = "J2" | IOSTAND
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Xilinx UG230 Spartan-3E FPGA Starter Kit Board User Guide

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