Xilinx UG230 Spartan-3E FPGA Starter Kit Board User Guide

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Chapter 8: PS/2 Mouse/Keyboard Port Keyboard organized differently for a mouse and keyboard. Furthermore, the keyboard interface allows bidirectional data transfers so the host device can illuminate state LEDs on the keyboard. The PS/2 bus timing appears in Table 8-2 and Figure 8-2. The clock and data signals are only driven when data transfers occur; otherwise they are held in the idle state at logic High. The timing defines signal requirements for mouse-to-host communications and bidirectional keyboard communications. As shown in Figure 8-2, the attached keyboard or mouse writes a bit on the data line when the clock signal is High, and the host reads the data line when the clock signal is Low. Table 8-2: PS/2 Bus Timing Symbol Parameter Min Max T CK Clock High or Low Time 30 μs 50 μs T SU Data-to-clock Setup Time 5 μs 25 μs T HLD Clock-to-data Hold Time 5 μs 25 μs CLK (PS2C) DATA (PS2D) TCK TCK Edge 0 Edge 10 T SU '0' start bit Figure 8-2: PS/2 Bus Timing Waveforms The keyboard uses open-collector drivers so that either the keyboard or the host can drive the two-wire bus. If the host never sends data to the keyboard, then the host can use simple input pins. A PS/2-style keyboard uses scan codes to communicate key press data. Nearly all keyboards in use today are PS/2 style. Each key has a single, unique scan code that is sent whenever the corresponding key is pressed. The scan codes for most keys appear in Figure 8-3. If the key is pressed and held, the keyboard repeatedly sends the scan code every 100 ms or so. When a key is released, the keyboard sends an “F0” key-up code, followed by the scan code of the released key. The keyboard sends the same scan code, regardless if a key has different shift and non-shift characters and regardless whether the Shift key is pressed or not. The host determines which character is intended. Some keys, called extended keys, send an “E0” ahead of the scan code and furthermore, they might send more than one scan code. When an extended key is released, an “E0 F0” key-up code is sent, followed by the scan code. 64 www.xilinx.com Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.2) January 20, 2011 T HLD '1' stop bit UG230_c8_02_021806 R
ESC 76 ` ~ 0E TA B 0D Caps Lock 58 Shift 12 Ctrl 14 R 1 ! 16 Q 15 F1 05 2 @ 1E W 1D A 1C Z 1Z F2 06 3 # 26 S 1B Alt 11 E 24 X 22 F3 04 4 $ 25 D 23 R 2D C 21 F4 0C 5 % 2E F 2B T 2C V 2A 6 ^ 36 F5 03 Y 35 G 34 B 32 7 & 3D Figure 8-3: PS/2 Keyboard Scan Codes Keyboard The host can also send commands and data to the keyboard. Table 8-3 provides a short list of some often-used commands. Table 8-3: Common PS/2 Keyboard Commands H 33 F6 0B U 3C N 31 Space 29 The keyboard sends commands or data to the host only when both the data and clock lines are High, the Idle state. Because the host is the bus master, the keyboard checks whether the host is sending data before driving the bus. The clock line can be used as a clear to send signal. If the host pulls the clock line Low, the keyboard must not send any data until the clock is released. The keyboard sends data to the host in 11-bit words that contain a ‘0’ start bit, followed by eight bits of scan code (LSB first), followed by an odd parity bit and terminated with a ‘1’ stop bit. When the keyboard sends data, it generates 11 clock transitions at around 20 to 30 kHz, and data is valid on the falling edge of the clock as shown in Figure 8-2. Spartan-3E FPGA Starter Kit Board User Guide www.xilinx.com 65 UG230 (v1.2) January 20, 2011 8 * 3E J 3B F7 83 M 3A I 43 9 ( 46 K 42 F8 0A O 44 , < 41 Command Description 0 ) 45 L 4B P 4D > . 49 F9 01 - _ 4E ; : 4C / ? 4A [ { 54 Alt E0 11 F10 09 = + 55 ' " 52 ] } 5B F11 78 Back Space 66 \ | 5D Enter 5A Shift 59 F12 07 E0 75 Ctrl E0 14 E0 74 E0 6B E0 72 UG230_c8_03_021806 ED Turn on/off Num Lock, Caps Lock, and Scroll Lock LEDs. The keyboard acknowledges receipt of an “ED” command by replying with an “FA”, after which the host sends another byte to set LED status. The bit positions for the keyboard LEDs are shown below. Write a ‘1’ to the specific bit to illuminate the associated keyboard LED. 7 6 5 4 3 2 1 0 EE Echo. Upon receiving an echo command, the keyboard replies with the same scan code “EE”. F3 Set scan code repeat rate. The keyboard acknowledges receipt of an “F3” by returning an “FA”, after which the host sends a second byte to set the repeat rate. FE Resend. Upon receiving a resend command, the keyboard resends the last scan code sent. FF Reset. Resets the keyboard. Ignored Caps Lock Num Lock Scroll Lock
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Spartan-3E FPGA Starter Kit Board U
Page 3 and 4:
Table of Contents Preface: About Th
Page 5 and 6:
R Writing Data to the Display . . .
Page 7 and 8:
R UCF Location Constraints . . . .
Page 9 and 10:
R About This Guide Acknowledgements
Page 11 and 12:
R Introduction and Overview Chapter
Page 13 and 14: R Design Trade-Offs Design Trade-Of
Page 15 and 16: R Switches, Buttons, and Knob Slide
Page 17 and 18: R Rotary Push-Button Switch In some
Page 19 and 20: A Rotating RIGHT B Detent R Discret
Page 21 and 22: R Clock Sources Overview Chapter 3
Page 23 and 24: R Clock Period Constraints Related
Page 25 and 26: R FPGA Configuration Options Chapte
Page 27 and 28: R Configuration Mode Jumpers The co
Page 29 and 30: R Programming the FPGA, CPLD, or Pl
Page 41 and 42: R Related Resources Figure 4-26: PR
Page 43 and 44: R Character LCD Screen Overview Cha
Page 45 and 46: R UCF Location Constraints LCD Cont
Page 47 and 48: R LCD Controller The character ROM
Page 49 and 50: R Disabled If the LCD_E enable sign
Page 51 and 52: R Table 5-4: Shift Patterns Accordi
Page 53 and 54: R Operation The data values on SF_D
Page 55 and 56: R VGA Display Port 1 2 3 4 5 6 11 7
Page 57 and 58: time HS R Current through the horiz
Page 59 and 60: R UCF Location Constraints Related
Page 61 and 62: R RS-232 Serial Ports Overview Chap
Page 63: R PS/2 Mouse/Keyboard Port Chapter
Page 67 and 68: R Voltage Supply UCF Location Const
Page 69 and 70: R Digital to Analog Converter (DAC)
Page 71 and 72: R Table 9-2: Disabled Devices on th
Page 73 and 74: R UCF Location Constraints Related
Page 75 and 76: R Analog Capture Circuit Chapter 10
Page 77 and 78: R Programmable Pre-Amplifier Finall
Page 79 and 80: R Analog to Digital Converter (ADC)
Page 81 and 82: R Disable Other Devices on the SPI
Page 83 and 84: R Chapter 11 Intel StrataFlash Para
Page 85 and 86: R Table 11-1: FPGA-to-StrataFlash C
Page 87 and 88: R Shared Connections Character LCD
Page 89 and 90: R Control Setting the FPGA Mode Sel
Page 91 and 92: R SPI Serial Flash UCF Location Con
Page 93 and 94: R Creating an SPI Serial Flash PROM
Page 95 and 96: R Configuring from SPI Flash Figure
Page 97 and 98: R Configuring from SPI Flash To gen
Page 99 and 100: R Insert Jumper on JP8 and Hold PRO
Page 101 and 102: R Other SPI Flash Control Signals A
Page 103 and 104: R Related Resources Related Resourc
Page 105 and 106: R DDR SDRAM 5.0V LTC3412 Chapter 13
Page 107 and 108: R Table 13-1: FPGA-to-DDR SDRAM Con
Page 109 and 110: R Control Related Resources Figure
Page 111 and 112: R Chapter 14 10/100 Ethernet Physic
Page 113 and 114: R MicroBlaze Ethernet IP Cores Tabl
Page 115 and 116:
R Expansion Connectors Chapter 15 T
Page 117 and 118:
R Table 15-1: Hirose 100-pin FX2 Co
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R Table 15-2: Differential I/O Pair
Page 121 and 122:
R Using Differential Outputs Hirose
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R Six-Pin Accessory Headers Header
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R Connectorless Debugging Port Land
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R XC2C64A CoolRunner-II CPLD Chapte
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R UCF Location Constraints UCF Loca
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R DS2432 1-Wire SHA-1 EEPROM UCF Lo
Page 133 and 134:
Schematics R This appendix provides
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R FX2 Expansion Header, 6-pin Heade
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R Figure A-2: Schematic Sheet 2 RS-
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R Figure A-3: Schematic Sheet 4 Eth
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R Figure A-4: Schematic Sheet 5 Vol
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R FPGA Configurations Settings, Pla
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R Figure A-6: Schematic Sheet 7 FPG
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R Figure A-7: Schematic Sheet 8 FPG
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R Figure A-8: Schematic Sheet 9 Pow
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R Figure A-9: Schematic Sheet 10 XC
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R Figure A-10: Schematic Sheet 11 L
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R Intel StrataFlash Parallel NOR Fl
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R Buttons, Switches, Rotary Encoder
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R DDR SDRAM Series Termination and
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R Appendix B Example User Constrain
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R NET "FX2_IO" LOC = "A16" | IOSTAN
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R NET "SD_LDM" LOC = "J2" | IOSTAND
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Xilinx UG230 Spartan-3E FPGA Starter Kit Board User Guide

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