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[49] C. Hansen, “Hardware logic simulation by compilation,” In Proceedings of the Design Automation Conference (DAC). SIGDA, ACM, 1988. [50] D. Harel, “Statecharts: A Visual Formalism for Complex Systems,” Sci. Comput. Program., vol 8, pp. 231-274, 1987. [51] P. G. Harrison, “A Higher-Order Approach to Parallel Algorithms,” The Computer Journal, Vol. 35, No. 6, 1992. [52] T. A. Henzinger, B. Horowitz and C. M. Kirsch, “Giotto: A Time-Triggered Language for Embedded Programming,” EMSOFT 2001, Tahoe City, CA, Springer-Verlag, [53] T. A. Henzinger, “The theory of hybrid automata,” in Proceedings of the 11th Annual Symposium on Logic in Computer Science, IEEE Computer Society Press, 1996, pp. 278-292, invited tutorial. [54] T.A. Henzinger, and O. Kupferman, and S. Qadeer, “From prehistoric to postmodern symbolic model checking,” in CAV 98: Computer-aided Verification, pp. 195-206, eds. A.J. Hu and M.Y. Vardi, Lecture Notes in Computer Science 1427, Springer-Verlag, 1998. [55] T. A. Henzinger and C. M. Kirsch, “The Embedded Machine: Predictable, portable real-time code,” In Proceedings of Conference on Programming Language Design and Implementation (PLDI). SIGPLAN, ACM, June 2002. [56] C. Hewitt, “Viewing control structures as patterns of passing messages,” Journal of Artificial Intelligence, 8(3):323–363, June 1977. [57] M. G. Hinchey and S. A. Jarvis, Concurrent Systems: Formal Developments in CSP, McGraw- Hill, 1995. [58] C. W. Ho, A. E. Ruehli, and P. A. Brennan, “The Modified Nodal Approach to Network Analysis,” IEEE Tran. on Circuits and Systems, Vol. CAS-22, No. 6, 1975, pp. 504-509. [59] C. A. R. Hoare, “Communicating Sequential Processes,” Communications of the ACM, Vol. 21, No. 8, August 1978. [60] C. A. R. Hoare, Communicating Sequential Processes, Prentice-Hall, 1985. [61] IEEE DASC 1076.1 Working Group, “VHDL-A Design Objective Document, version 2.3,” http:/ /www.vhdl.org/analog/ftp_files/requirements/DOD_v2.3.txt [62] D. Jefferson, Brian Beckman, et al, “Distributed Simulation and the Time Warp Operating System,” UCLA Computer Science Department: 870042, 1987. [63] G. Kahn, “The Semantics of a Simple Language for Parallel Programming,” Proc. of the IFIP Congress 74, North-Holland Publishing Co., 1974. [64] G. Kahn and D. B. MacQueen, “Coroutines and Networks of Parallel Processes,” Information Processing 77, B. Gilchrist, editor, North-Holland Publishing Co., 1977. [65] G. Karsai, M. Maroti, Á. Lédeczi, J. Gray and J. Sztipanovits, “Type Hierarchies and Composition in Modeling and Meta-Modeling Languages,” IEEE Transactions on Control System Technology, to appear, 2004. [66] G. Karsai, “A Configurable Visual Programming Environment: A Tool for Domain-Specific Programming,” IEEE Computer: 36-44, March 1995, 1995. 248 Ptolemy <strong>II</strong>
[67] E. Kohler, The Click Modular Router, Ph.D. Thesis, Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, February 2001. [68] H. Kopetz, Real-Time Systems: Design Principles for Distributed Embedded Applications, Kluwer Academic Publishers, 1997. [69] P. Laramie, R.S. Stevens, and M.Wan, “Kahn process networks in Java,” ee290n class project report, Univ. of California at Berkeley, 1996. [70] D. Lea, Concurrent Programming in Java TM , Addison-Wesley, Reading, MA, 1997. [71] B. Lee and E. A. Lee, “Interaction of Finite State Machines with Concurrency Models,” Proc. of Thirty Second Annual Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, California, November 1998. (http://ptolemy.eecs.berkeley.edu/publications/papers/98/Interaction- FSM/) [72] B. Lee and E. A. Lee, “Hierarchical Concurrent Finite State Machines in Ptolemy,” Proc. of International Conference on Application of Concurrency to System Design, p. 34-40, Fukushima, Japan, March 1998 (http://ptolemy.eecs.berkeley.edu/publications/papers/98/HCFSMinPtolemy/) [73] E. A. Lee and S. Neuendorffer, “Classes and Subclasses in Actor-Oriented Design,” In Proceedings of Conference on Formal Methods and Models for Codesign (MEMOCODE), San Diego, CA, USA, June 22-25, 2004. [74] E. A. Lee and Y. Xiong, “A Behavioral Type System and Its Application in Ptolemy <strong>II</strong>,” Formal Aspects of Computing Journal, special issue on Semantic Foundations of Engineering Design Languages, to appear, 2004. [75] E. A. Lee, S. Neuendorffer and M. J. Wirthlin, “Actor-Oriented Design of Embedded Hardware and Software Systems,” Journal of Circuits, Systems, and Computers, 12(3): 231-260, 2003, 2003. [76] E. A. Lee, “Embedded Software,” in Advances in Computers (M. Zelkowitz, editor), Vol. 56, Academic Press, London, 2002. [77] E. A. Lee, “What's Ahead for Embedded Software?” IEEE Computer, September 2000, pp. 18-26. [78] E. A. Lee, “Modeling Concurrent Real-time Processes Using Discrete Events,” Invited paper to Annals of Software Engineering, Special Volume on Real-Time Software Engineering, Volume 7, 1999, pp 25-45. Also UCB/ERL Memorandum M98/7, March 4th 1998.(http://ptolemy.eecs.berkeley.edu/publications/papers/98/realtime) [79] E. A. Lee and Y. Xiong, “System-Level Types for Component-Based Design,” First Workshop on Embedded Software, EMSOFT 2001, Lake Tahoe, CA, USA, Oct. 8-10, 2001. (also Technical Memorandum UCB/ERL M00/8, Electronics Research Lab, University of California, Berkeley, CA 94720, USA, February 29, 2000. http://ptolemy.eecs.berkeley.edu/publications/papers/01/systemLevelType/). [80] E. A. Lee, “Computing for Embedded Systems,” invited paper, IEEE Instrumentation and Measurement Technology Conference, Budapest, Hungary, May 21-23, 2001. [81] E. A. Lee and T. M. Parks, “Dataflow Process Networks,”, Proceedings of the IEEE, vol. 83, no. 5, pp. 773-801, May, 1995. (http://ptolemy.eecs.berkeley.edu/publications/papers/95/processNets) Heterogeneous Concurrent Modeling and Design 249
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PTOLEMY II HETEROGENEOUS CONCURRENT
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VOLUME 1 INTRODUCTION TO PTOLEMY II
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Volume 1 Contents Introduction to P
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2.10.3. Constructing Modal Models 8
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7. MoML 191 7.1. Introduction 191 7
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1 Introduction Author: Edward A. Le
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Introduction heterochronous dataflo
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Introduction A major emphasis in Pt
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Introduction determine when actors
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Introduction provides levels of vis
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Introduction is a guard, and the se
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Introduction well. All of these are
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Introduction clients to update thei
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Introduction will be supplied with
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Introduction 1.3.12 Synchronous Dat
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Introduction FIGURE 1.10. Refinemen
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Introduction occlusions due to terr
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Introduction tion. The overall arch
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Introduction kernel.attributes This
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Introduction 1.5.2 Overview of Key
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Introduction Actor interfaces are k
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Heterogeneous Concurrent Modeling a
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Introduction actor actor.gui data.e
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Introduction cient, scalable, and u
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Introduction 1.5.8 Future Capabilit
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Introduction Appendix A: UML — Un
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Introduction grams, the only constr
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2 Using Vergil Authors: Edward A. L
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Using Vergil 2.2.2 Executing a Pre-
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Using Vergil The Lorenz attractor m
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Using Vergil The Continuous-Time (C
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Using Vergil box in figure 2.11. En
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Using Vergil Don’t panic! Excepti
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Using Vergil tions are a normal par
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Using Vergil 2.4 Hierarchy Ptolemy
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Using Vergil Then using these ports
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Using Vergil the default 0.1 to 0.0
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Using Vergil pan window, it is easy
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Using Vergil FIGURE 2.33. The pan w
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Using Vergil we have modified the c
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Using Vergil model, simply copy (or
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Using Vergil A key issue is to deci
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Using Vergil instances. This proble
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Using Vergil quick tour for more de
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Using Vergil uses the index in the
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Using Vergil AddSubtract actor, and
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Using Vergil If you look inside the
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Using Vergil If you look inside the
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Using Vergil transition (or right c
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Using Vergil Once you have created
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Using Vergil The grid is turned off
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Authors: Edward A. Lee Xiaojun Liu
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Expressions classes to create a gen
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Expressions The % operation is a mo
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Expressions attribute, which includ
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Expressions 3.3.5 State Machines Ex
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Expressions whose value is an array
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Expressions from it. For instance,
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Expressions defined. For example, >
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Expressions length is given by the
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Expressions Thus, for example, you
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Expressions number. With one additi
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Expressions value. For example, fix
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Expressions In the example in figur
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Expressions A.2 Basic Mathematical
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Expressions A.3 Matrix, Array, and
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Expressions A.5 Signal Processing F
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Expressions TABLE 8: Functions perf
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4 Actor Libraries Authors: Elaine C
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Actor Libraries properly in the CT
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Actor Libraries ing that multiple c
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Actor Libraries TypedAtomicActor «
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Actor Libraries SequenceScope (exte
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Actor Libraries UnsignedByteArrayTo
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Actor Libraries MobileFunction (ext
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Actor Libraries LogicFunction (exte
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Actor Libraries Sleep (extends Tran
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Actor Libraries VariableFIR (extend
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Actor Libraries Integrator: Integra
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Actor Libraries Figure 4.4 shows th
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5 Designing Actors Authors: Christo
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Designing Actors /** Javadoc commen
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Designing Actors although with most
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Designing Actors import ptolemy.act
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Designing Actors makes such actors
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Designing Actors same parameter val
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Designing Actors morphic actor comp
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Designing Actors To get data polymo
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Designing Actors public class Seque
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Designing Actors be used in domains
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Designing Actors alComm actor. Beca
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Designing Actors attribute has valu
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Designing Actors import ptolemy.act
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6 Coding Style Authors: Christopher
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Coding Style /* One line descriptio
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Coding Style Copyright (c) 2004 The
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Coding Style @version $Id: NamedObj
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Coding Style } We use instead the i
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Coding Style * @exception MyExcepti
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Coding Style + "it does not impleme
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Authors: Edward A. Lee Steve Neuend
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MoML cutes it forever, until you hi
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MoML A second difference between ou
Page 207 and 208: MoML
Page 209 and 210: MoML 7.3.3 Names and Classes Most M
Page 211 and 212: MoML Here, the element named
Page 213 and 214: MoML implement. 7.3.7 Doc Element S
Page 215 and 216: MoML It is also sometimes necess
Page 217 and 218: MoML then there will be a link t
Page 219 and 220: MoML found. For example, if the cla
Page 221 and 222: MoML it cannot collide with the nam
Page 223 and 224: MoML The rendering of the icon is d
Page 225 and 226: MoML 7.4.5 Deleting Entities, Relat
Page 227 and 228: MoML This unlinks a port from the s
Page 229 and 230: MoML model. The EntityLibrary class
Page 231 and 232: MoML Suppose that using incremental
Page 233 and 234: MoML Generate a sine wave.
Page 235 and 236: MoML
Page 237 and 238: MoML Number of iterations in
Page 239 and 240: MoML -P- The f
Page 241 and 242: MoML -P- The phase,
Page 243 and 244: 8 Custom Applets Authors: Edward A.
Page 245 and 246: Custom Applets html code, see the J
Page 247 and 248: Custom Applets public class Tutoria
Page 249 and 250: Custom Applets then the result of
Page 251 and 252: Custom Applets 8.3.5 Using Model Pa
Page 253 and 254: Custom Applets ptolemy/domains/doma
Page 255 and 256: References [1] G. Agha, Actors: A M
Page 257: [33] S. A. Edwards, “The Specific
Page 261 and 262: [95] J. Liu, X. Liu, T. J. Koo, B.
Page 263 and 264: [132]W. R. Sutherland, "The on-Line
Page 265 and 266: Glossary abstract syntax ..........
Page 267 and 268: Ptolemy II ........................
Page 269 and 270: Index Symbols - in UML 41 # in UML
Page 271 and 272: coin flips 142 Color class 173 colo
Page 273 and 274: entity in XML 198 EntityLibrary cla
Page 275 and 276: Director class 159 inverse FFT 124
Page 277 and 278: CompositeEntity class 206 nextPower
Page 279 and 280: safety 34 SampleDelay actor 78, 138
Page 281 and 282: type constraint 155 type constraint
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